Short-circuit Stress Research Articles

Methodology for Characterizing Degradation Locations of Planar and Trench Gate SiC Power Mosfets Under Repetitive Short-Circuit Stress

Methodology for Characterizing Degradation Locations of Planar and Trench Gate SiC Power Mosfets Under Repetitive Short-Circuit Stress

Study of the Short-Circuit Capability and Device Instability of p-GaN Gate HEMTs by Repetitive Short-Circuit Stress

Study of the Short-Circuit Capability and Device Instability of p-GaN Gate HEMTs by Repetitive Short-Circuit Stress

Study on short circuit effect of silicon carbide power devices

SiC can provide better material properties when the performance of Si - based power devices is almost developed to the limit. But compared with Si material, the reliability of SiC device is poor under ultimate stress. The short circuit capability of SiC MOSFET has been the main area of attention in this papers study. Through the analysis of SiC MOSFET short-circuit capability, it is mainly represented by the time that the device can withstand short-circuit stress and the time it takes for the device to be safely turned off in the event of a short circuit fault. Secondly, the detection circuit and protection circuit under the SiC MOSFET short-circuit fault are briefly studied, and the optimization ideas and working principles are summarized.

Failure degradation similarities on power SiC MOSFET devices submitted to short-circuit stress and accelerated switching conditions

The aim of this paper is to present a comparison between failure analyses results performed on power SiC devices. Various devices have been submitted to SC (Short-circuit) stress and ITASC (Inverter Test with Accelerated Switching Conditions) method. Some similarities have been detected, as well as the same failure mode represented by a gate-source shorted-circuit.

Review on the Reliability Mechanisms of SiC Power MOSFETs: A Comparison Between Planar-Gate and Trench-Gate Structures

To clarify the current research situation and offer a better understanding of the reliability for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs), a comparison among the reliability mechanisms between planar-gate and trench-gate SiC power MOSFETs, which have not been comprehensively summarized, is made in this work. The latest studies focusing on the reliability issues of commercial SiC MOSFET products, including the planar-gate device, the double-trench device and the asymmetric trench-gate device, are reviewed. For the existing of the gate trenches and the unique structures protecting them, SiC trench-gate MOSFETs express quite different instability phenomena from the planar-gate ones under various ultimate and long-term electro-thermal stresses. The influences of these stresses closely related to the practical operation conditions on SiC power MOSFETs, including the avalanche stress, the short-circuit (SC) stress, the surge current stress of the body diode, and the switching stress, are discussed and reviewed in details.

Investigation on safe-operating-area degradation and failure modes of SiC MOSFETs under repetitive short-circuit conditions

• Repetitive short circuits cause thermal runaway failure of SiC MOSFETs • Safe operating area reduces after repetitive short-circuit conditions • Repetition frequency and duration affect degradation of SiC MOSFETs • Hole traps in gate oxides induce degradation of SiC MOSFETs The safe operating area is an operating area with high reliability for SiC MOSFET, and its degradation may cause power electronic system failure. The safe-operating-area degradation and the failure modes of 1200V/66A SiC MOSFET caused by repetitive short-circuit stress with different short-circuit times and short-circuit time intervals are investigated. A short circuit test platform with circuit protection is configured to degrade DUT(device under test), and the safe operating area is characterized after repetitive short circuit stress is applied. The degradation mechanism of the safe operating area is explained by the 1-D electro-thermal coupling model based on Sentaurus TCAD. When the critical short-circuit duration is 12μs, the single short-circuit failure mode of DUT with 400V dc-bus voltage is a gate-source short-circuit failure. From the short circuit test result, the failure modes under repetitive short-circuit conditions include gate-source short-circuit failure and thermal runaway, depending on the repetitive short-circuit time intervals. For the same short-circuit time interval, when the short-circuit duration is 10μs, the weakest boundary of the safe operating area is the blocking voltage. When the short-circuit duration is 2μs, all three boundaries of the safe operating area are contracted. These results are confined to 400V dc-bus voltage, 25°C case temperature, and 18V/-3V gate-source voltage. Schematic diagram of the degradation of the safe operating area of the device under long-term operating conditions. (a) Small margin, failure (b) Large margin, high cost (c) Optimal design

Predictive gate ageing-laws of SiC MOSFET under repetitive short-circuit stress

This paper proposes SiC MOSFET gate ageing-laws under repetitive short-circuit stress. Based on analytical studies, physical forms and preconditioning data, numerical fitting based on stress variables ΔTj, TPulse Gate Damage % and Esc is proposed. Accuracy and prediction capabilities of ageing-laws have been evaluated and compared. Resulting in suggesting a new ageing-law based on ΔTAl_Top metal-source. This one gives the best fitting accuracy. Finally, the ageing-law based directly on the short-circuit energy Esc appears to have the best in prediction capability.

Gate Bias Dependence of V TH Degradation in Planar and Trench SiC MOSFETs Under Repetitive Short Circuit Tests

The reliability of SiC MOSFETs under harsh operating conditions, such as short circuit (SC) stress, remains a major concern. In this article, a dedicated aging platform is developed to study the degradation of SiC planar- and trench-gate MOSFETs under repetitive SC conditions. The static characteristics of the devices are monitored in real-time during the test. Depending on the gate bias used in the experiments, a bidirectional <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shift in both types of devices is observed, yet with a different degradation rate. The underlying degradation mechanisms investigated by device simulation reveal that the damaged region in the SiC planar-gate MOSFET is located near the channel area, while at the trench corner in the SiC trench-gate MOSFET. These research outcomes enable better understanding of the degradation mechanisms of different SiC MOSFET structures and possible ruggedness improvements in the future.

Effect of diode arc-back fault on short circuit stress of power converter transformer✰

In polypropylene petrochemical plants power adjustable speed drives (ASDs) are normally used to drive extruder or pump machines required by this type of industrial process. Each one of these ASDs is fed by a dedicated converter transformer which supplies a diode-front-end rectifier in the input converter part of the ASD. In case one diode of the input rectifier is faulted and becomes short-circuited, the converter transformer can be subjected to a dynamic short circuit stress being higher than that due to a fault occurring just at transformer terminals: this phenomenon is called diode arc-back fault in technical literature. Simulations are carried out by means of EMTP-ATP software in order to show the effect of diode arc-back fault on the dynamic peak short circuit currents to which transformer windings are exposed

Short-Circuit Capability Prediction and Failure Mode of Asymmetric and Double Trench SiC MOSFETs

In this article, short-circuit capability prediction and failure mode of 1200-V-class SiC MOSFETs with a double and asymmetric trench structure are proposed under single-pulse short-circuit stress. A short-circuit prediction model is established to evaluate short-circuit withstand time and corresponding critical energy of devices under various dc bus voltages. This model can provide quick predictive guidance even if there are few test results, and the predicted values are consistent with practical values. Furthermore, two failure modes are investigated in a short-circuit test. For asymmetric trench SiC MOSFETs, failure modes are gate damage at lower dc bus voltages and thermal runaway at higher dc bus voltages; whereas failure mode for double trench SiC MOSFETs is thermal runaway at all dc bus voltages. In addition, the internal thermal-electro stress of the device is analyzed until it fails during short-circuit condition, and proves that failure mode depends on the dc bus voltage and peak short-circuit current of the device. Finally, the top view of failed devices confirms the two failure modes of trench SiC MOSFETs by the postdecapsulation.

Eliminating Repetitive Short-Circuit Degradation and Failure of 1.2-kV SiC Power MOSFETs

Silicon carbide (SiC) power MOSFETs are known to degrade and eventually fail under repetitive short-circuit (SC) stress. In this article, a new approach, named Baliga Short-Circuit Improvement Concept (BaSIC) depletion-mode MOSFET (DMM), is demonstrated to prevent the degradation and failure of 1.2-kV SiC power MOSFETs under repetitive SC stress. The new concept utilizes a low-voltage, gate–source-shorted Si DMM connected to the source of the SiC MOSFET. It was experimentally verified that no degradation or failure of the SiC power MOSFET occurs after over 3000 SC events with the BaSIC(DMM) topology while the SiC power MOSFETs degraded and failed after 200 SC events without it.

Analysis of trap and recovery characteristics based on low-frequency noise for E-mode GaN HEMTs with p-GaN gate under repetitive short-circuit stress

In this letter, the degradation and recovery characteristics of E-mode AlGaN/GaN high-electron mobility transistors (HEMTs) were investigated under repetitive short-circuit (SC) stress. Output, transfer, transconductance and gate-leakage characteristics were analyzed in detail before and after repetitive SC stress. After stress, the electrical characteristics of the devices gradually degraded as the SC pules increased. Low-frequency noise measurements are performed over the frequency range of 1 Hz–10 KHz by increasing SC pulses. Furthermore, the recovery tendency of DC characteristics and trap density is observed between repetitive SC measurements, and this physically confirms that the mechanism of the performance degradation could be attributed to the trapping and releasing processes of electrons in the p-GaN layer and AlGaN barrier layer of AlGaN/GaN HEMTs, which change the electric field distribution under the gate.

Trap Analysis Based on Low-Frequency Noise for SiC Power MOSFETs Under Repetitive Short-Circuit Stress

In this paper, the degradation behavior of the electrical characteristics was investigated, and trap analysis based on low-frequency noise (LFN) was carried out for the commercial 1.2-kV /30-A silicon carbide (SiC) power MOSFETs under repetitive short-circuit (SC) stress. The experiment results show that the on-state resistance ( ${R} _{\mathrm{ dson}}$ ) and threshold voltage ( ${V} _{\mathrm{ th}}$ ) increase significantly. Meanwhile, the drain-source current ( ${I} _{\mathrm{ ds}}$ ) decreases obviously with the increase of the SC cycles. Furthermore, the gate-source leakage current ( ${I} _{\mathrm{ gss}}$ ) of the SiC power MOSFETs increase greatly and the blocking characteristics deteriorated after 1000 SC cycles. The positive shift was observed on the gate-capacitance versus gate-voltage ( ${C} _{\mathrm{ g}}$ - ${V} _{\mathrm{ g}}$ ) curve, which shows that the damage region could be in channel along the SiC/SiO2 interface after repetitive SC stress. In order to obtain the trap information, trap characterization was performed by using LFN method, and the LFN results show that the trap density increases with the SC cycles. The physical mechanism could be attributed to electrically active traps generated at SiC/SiO2 interface and oxide layer due to the peak ionization rate, the perpendicular electrical field and high temperature during SC stress. The study may be useful to provide reference for converters design and fault protection of SiC power MOSFETs.

Implications of short-circuit events on power cycling of 1.2-kV/20-A SiC MOSFET power modules

When the device works in the real-field application, short-circuit events could happen along the whole lifetime of the component. In order to investigate the degradation effects of short-circuit events on power cycling, a mixed accelerated aging test combined with a repetitive short-circuit test has been performed for the 1.2-kV/20-A SiC MOSFET power module. The short-circuit robustness and repetitive short-circuit performance are analysed on the fresh device at first in order to understand the different levels of degradation. Then, the power cycling test is performed for two matched devices with the selected test conditions; one of them undergoes a number of short-circuit events and the other one, without short-circuit stress, is used as the reference. The experimental results exhibit a major implication of short-circuit degradation on power cycling and it would accelerate the degradation process of SiC MOSFETs.

Comprehensive Analysis of Electrical Parameters Degradations for SiC Power MOSFETs Under Repetitive Short-Circuit Stress

The degradations of electrical parameters for silicon carbide power MOSFETs under repetitive short-circuit (SC) stress are investigated in detail in this paper. It demonstrates that the generation of negative charges along the gate–oxide interface of the channel region is the dominant degradation mechanism, which results in the increase in the threshold voltage ( ${V}_{\text {th}}$ ) and the rise of ON-state resistance ( ${R}_{\text {dson}}$ ) under low gate voltage bias condition. Furthermore, degradations of dynamic characteristics including gate charge ( ${Q}_{\text {g}}$ ) and switching behaviors of the device after the repetitive SC stress are extracted and analyzed for the first time. It illustrates that the increased ${V}_{\text {th}}$ contributes to the rise of the Miller plateau voltage ( ${V}_{\text {gp}}$ ), which further leads to the increase in gate–source charge ( ${Q}_{\text {gs}}$ ). Meanwhile, the increase in the turn-ON time and the reduction of turn-OFF time are observed, which are also resulted from the positive shifts of ${V}_{\text {th}}$ and ${V}_{\text {gp}}$ , leading to the rise of turn-ON switching energy ( ${E}_{{ \text {on}}}$ ) and the decline of turn-OFF switching energy ( ${E}_{\text {off}}$ ), respectively.

Effect of short-circuit stress on the degradation of the SiO2 dielectric in SiC power MOSFETs

This paper presents the impact of a short-circuit event on the gate reliability in planar SiC MOSFETs, which becomes more critical with increased junction temperature and higher bias voltages. The electrical waveforms indicate that a gate degradation mechanism takes place, showing a large gate leakage current that increases as the gate degrades more and more. A failure analysis has been performed on the degraded SiC MOSFET and then compared to the structure of a new device to identify possible defects/abnormalities. A Focused-Ion Beam cut is performed showing a number of differences in comparison to the new device: (i) cracks between the poly-silicon gate and aluminium source, (ii) metal particles near the source contact, and (iii) alterations in the top surface of the aluminium source. The defects have been correlated with the increase in gate-leakage current and drain-leakage current.

Short-Circuit Robustness Testing of SiC MOSFETs

This paper presents electrical results for two different commercial devices and one prototype 1.2 kV SiC power MOSFET device subject to short-circuit (SC) stress. Two failure modes were observed among the devices tested, with one mode of failure resulting in catastrophic device destruction and the other resulting in permanent damage of the insulating gate dielectric manifested as a leakage current of 400 mA. Short-circuit pulses of increasing time duration caused a reduction in the gate-to-source voltage toward the falling edge of the pulse. This phenomenon is a precursor to failure of SiC MOSFETs under SC stress, but this reduction in VGS is not known to occur in silicon-based devices. The measured short-circuit withstand times for commercial devices from group A and B MOSFETs were 8 us and 12 us, respectively. MOSFET-C devices had a withstand time of 7 us. A larger chip size improves robustness even for large values of peak short-circuit current.

Short-circuit stress calculation in oval windings

In this paper an analytical approach for calculation of mechanical strength of oval windings in distribution transformers is presented. The calculation is given for radial forces resulting from interaction of the axial component of leakage flux density and the current in the windings. The analysis is focused on the inner foil winding subjected to radial forces acting inwards where winding could fail either by collapsing or by bending between the supports. The most common failure mode is free buckling where foil conductors (usually outer half of low voltage winding) bulge outwards as well as inwards usually at one specific point along the circumference.

Short Circuit Stress Analysis Using FEM in Power Transformer on H-V Winding Displaced Vertically & Horizontally

The aim of this work was to work out the mechanical stresses within transformer resulting from the extreme short-circuit currents. The forces and stresses set up in transformer windings as the result of exterior or interior short-circuits or of switching operations, are measured in detail. A variety of arrangements of windings in large power transformers are described. Points at which mostly high mechanical stresses take place in concentric windings are discussed in detail. Analytical and FEM calculations for individual short circuit forces, axial and radial have been discussed. The result was then compared with actual measurements on a prototype 20MVA 132/11.5kV power transformer [15]. Various failure mechanisms due to these forces have been discussed. Design parameters are also discussed, whose values determine the maximum stresses which may occur in any part of the transformer. Effects of irregularity in various parts and various properties of materials have been studied and the usage of appropriate material for withstanding the dynamic effects of SC is discussed. Effect of workmanship errors on short circuit withstand capability has also elucidated. Finally, a complete model is developed.

Determination of short circuit stresses in an air core reactor using finite element analysis

This paper shows the use and effectiveness of finite element method while designing an air core reactor for determining the short circuit forces and stress level due to short circuit. A 500 Amp air core series reactor having nominal voltage rating of 600 Volt was to be designed and to be subjected to a short circuit current of 8 KA for 2 second. A finite element approach was adopted in designing the stress level due to short circuit forces and the results were utilized in developing a reactor that finally withstood the short circuit test.Keywords: Reactor, Short circuit forces, von Mises stress, Finite Element Method, Inductor