Short-circuit Failure Research Articles

Research and Application of Transient Transparent Sensing Technology in Substations Using Internet of Things to Distributely Connect Non-contact New Broadband Sensor

When the equipment in the substation undergoes major disturbances (such as short-circuit failure, system oscillation, frequency collapse, voltage collapse, line lightning intrusion, etc.), electrical quantities (voltage, current, frequency, etc.) will undergo transient changes. This process is to correctly analyze the accident. The basis of cause can be used to evaluate the operating status of equipment, find fault points, and quickly deal with faults. However, the current domestic transient information perception in substations still needs to be developed: 1) The existing system data sources are PT and CT data, which are restricted by the bandwidth of PT and CT, and the high-frequency monitoring accuracy is not high; 2) the construction and maintenance of centralized screens are complicated. Using a large number of secondary cables; 3) the redundancy is small, and it is not easy to increase and upgrade. Therefore, it is urgent to develop a new type of distributed substation transient information sensing technology, to develop a system wide-frequency transient current sensing technology based on advanced magnetic field sensors to achieve non-contact measurement, and to develop a system broadband transient based on advanced optical electric field sensors to achieve non-contact measurement.

Analysis of short-circuit failures in synchronous machinery rotor using finite elements

In this paper, a mathematical model using finite element software is developed. An electromagnetic analysis is performed to determine the behavior of quantities such as magnetic flux density and output voltage when short-circuit failures occur in the winding of the rotor poles of a synchronous small size machine when it works as a generator. The voltage values obtained from the simulations were compared with data from actual tests performed in the laboratory.

Transient Test and AC Loss Study of a Cryogenic Propulsion Unit for All Electric Aircraft

This paper reports a pioneering demonstration platform of a cryogenic propulsion unit at liquid nitrogen temperature. A high temperature superconducting (HTS) machine is connected with a cryogenic power rectifier in a generator mode to prove the feasibility of a cryogenic propulsion unit for electric aircraft propulsion applications. Machine operation was carried out with a special focus on the total heat dissipation inside the HTS AC windings. Different types of 2G HTS tapes were tested to provided data for stator coils’ design. The transient operation was carried out to represent a short-circuit failure in one of the power electronic devices. The test shows AC loss performance of the HTS windings using calorimetric method during the short circuit event, indicating the importance of developing protection schemes for the cryogenic propulsion units to prevent damage to the HTS components. The paper provides initial insights into the interaction between superconducting machines and cryogenic power electronics within a cryogenic propulsion unit. It is an important first step to understand and further develop cryogenic propulsion technology for future electric aircraft.

Short-Circuit Capability Prediction and Failure Mode of Asymmetric and Double Trench SiC MOSFETs

In this article, short-circuit capability prediction and failure mode of 1200-V-class SiC MOSFETs with a double and asymmetric trench structure are proposed under single-pulse short-circuit stress. A short-circuit prediction model is established to evaluate short-circuit withstand time and corresponding critical energy of devices under various dc bus voltages. This model can provide quick predictive guidance even if there are few test results, and the predicted values are consistent with practical values. Furthermore, two failure modes are investigated in a short-circuit test. For asymmetric trench SiC MOSFETs, failure modes are gate damage at lower dc bus voltages and thermal runaway at higher dc bus voltages; whereas failure mode for double trench SiC MOSFETs is thermal runaway at all dc bus voltages. In addition, the internal thermal-electro stress of the device is analyzed until it fails during short-circuit condition, and proves that failure mode depends on the dc bus voltage and peak short-circuit current of the device. Finally, the top view of failed devices confirms the two failure modes of trench SiC MOSFETs by the postdecapsulation.

Experimental Study on the Short-Circuit Failure Mechanism of Cumulative Discharge in Gas Discharge Tube

Gas discharge tube (GDT) breaks down discharge with surge overvoltage during long-term use. Notably, there is a risk of short-circuit failure due to the drop in insulation resistance after a certain number of discharges, which might be mainly caused by cumulative discharge. This article builds a cumulative discharge experiment platform to analyze the failure mechanism, performed the GDT whole life cycle cumulative discharge experiment and focused on the change law of its insulation resistance and breakdown voltage. For samples that are short-circuited, X-ray observation and vibration testing perpendicular to the GDT axis are conducted to examine the internal micro-morphology without damaging their external structure. The GDT is opened and its internal structure and material properties of the GDT cavity are compared and analyzed by scanning electron microscope (SEM) and energy dispersive spectroscopy (EDS) methods. The results indicated that the insulation resistance of GDT continuously decreased by several orders of magnitude in the last 10% of the life cycle, and the insulation resistance before failure is generally less than 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{k}\Omega $ </tex-math></inline-formula> . Through X-ray observation of the short-circuit failure sample, two different abnormal growth phenomena in the cavity are found, including flocs between the electrodes and deposits on the tube wall. Further analysis and experiments demonstrated that the flocs between the electrodes and the deposits on the tube wall are the primary factors causing the degradation of GDT insulation performance. The formation mechanism of the two short-circuit modes is explained by the difference in the splash angle and mode of metal particles of different sizes on the electrode surface.

Eliminating Repetitive Short-Circuit Degradation and Failure of 1.2-kV SiC Power MOSFETs

Silicon carbide (SiC) power MOSFETs are known to degrade and eventually fail under repetitive short-circuit (SC) stress. In this article, a new approach, named Baliga Short-Circuit Improvement Concept (BaSIC) depletion-mode MOSFET (DMM), is demonstrated to prevent the degradation and failure of 1.2-kV SiC power MOSFETs under repetitive SC stress. The new concept utilizes a low-voltage, gate–source-shorted Si DMM connected to the source of the SiC MOSFET. It was experimentally verified that no degradation or failure of the SiC power MOSFET occurs after over 3000 SC events with the BaSIC(DMM) topology while the SiC power MOSFETs degraded and failed after 200 SC events without it.

Analysis of electrical and thermal characteristics of PV array under mismatching conditions caused by partial shading and short circuit failure of bypass diodes

In this paper, the problems of PV arrays under partial shading and a short circuit failure of bypass diode were analyzed with modeling the mathematical equation by using simulation, and the electrical and thermal characteristics were analyzed in an outdoor with a module which fabricated assuming a real PV array. The simulation model shows the mismatch current due to a bypass diode failure is proportional to the number of fault diodes and parallel strings in PV arrays. From the results of a field experiment, a reverse current did not flow into the mismatching string under partial shading regardless of system operation status, but the temperature of bypass diode in the case of system operation was 15–23 °C higher than that of the other case. However, in case of the fault bypass diode with the system off, the reverse current of 17A flowed into a fault string. Besides, the surface temperature of fault bypass diode reached above 140 °C, and some solar cells within a fault string was 18 °C higher than normal strings. In this paper, we verified that the short circuit failure of bypass diode creates a mismatch loss in PV system, and the reverse current causes electric-thermal problems in PV array.

Determination of failure degree of 1.2 kV SiC MOSFETs after short-circuit test using an improved test setup

Abstract Analysis of the short-circuit characteristics of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) is very important for their practical application. This paper studies the SiC MOSFET short-circuit characteristics with an improved test setup under different conditions. A high-current Si insulated gate bipolar transistor is used as a circuit breaker in the test circuit rather than the usual short-circuit test conducted without a circuit breaker. The test platform with a circuit breaker does not influence the calculation results regarding the short-circuit withstand time and energy, but the SiC MOSFET will switch off after failure in a very short time. In addition, the degree of failure will be limited and confined to a small area, such that the damage to the chip will be clearly observable, which is significant for short-circuit failure analysis.

Investigation on Short-Circuit Characterization and Optimization of 3.3-kV SiC MOSFETs

The short-circuit (SC) ruggedness of 3.3-kV silicon carbide (SiC) MOSFETs is of great importance for traction applications. In this article, the SC characterization and failure mechanism of 3.3-kV planar-gate SiC MOSFETs are systematically studied by experiments and simulations. The measured SC withstanding time (SCWT) of 3.3-kV SiC MOSFETs is about 17 μs, and the SC energy density is 15.5 J/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Research demonstrates that the current clamping phenomenon is attributed to the high density of interface traps (Dit) in the gate oxide of 3.3-kV SiC MOSFETs. Furthermore, the positive temperature feedback mechanism and the triggering of parasitic n-p-n transistor are proved to cause the SC failure. At last, three optimized cell structures are proposed for improving the SC capability of 3.3-kV SiC MOSFETs, where the optimal SCWT is enhanced by 23% without degrading the forward conduction capability.

(Keynote) The Role of Interlayer Chemistry in Li-Metal Growth through a Garnet-Type Solid Electrolyte

Although garnet-type LLZO has been considered one of the most promising solid electrolyte for solid-state batteries (SSB), the instability of electrode/LLZO interface has been obstacle for the practical application of LLZO into the batteries.[1] Thus, a fundamental understanding of the lithium deposition behavior in the interface would aid in elucidating the underlying mechanisms of the short circuit failure due to unstable interface and designing the interface in SSBs. Herein, we successfully used an in operando microscopy technique to probe Li deposition through the LLZO electrolyte in an anode-free solid-state battery setup. More importantly, we carefully examined the interface with artificial interlayers, which revealed that Li plating is strongly dominated by the kinetics of alloying and precipitation through the metal interlayer. In addition, we confirmed that the interlayer also affects the sequential stripping process, influencing the electrochemical performance of the cell. Supported by these intriguing observations, we propose the dynamic roles of the interlayer during battery operation: as a buffer layer and a seed layer.The in-house cell and microscope system shown in Figure 1a were used for the in operando observations of Li deposition on LLZO. Li foil was attached to the bottom of the LLZO pellet and the top surface was pre-coated with the selected interlayer metal. We investigated electrochemical Li deposition behavior in the absence of an interlayer metal. Li metal begins to appear in island shapes under an applied galvanostatic current (0.1 mA cm-2) and continues to grow over time as shown in Figure 1b. It is worth noting that all of the small Li-metal islands first form at pre-existing defects on the pristine LLZO surface during initial lithiation and Li grows preferably at these islands during the subsequent plating. When the metal interlayer was introduced, the deposition behavior was significantly altered. With 30-nm-thick Au layer, we observed that Au interlayer changed color under electrochemical bias, which is indicative of the formation of a Li-Au alloy. These color changes are followed by the formation of island-type small precipitations. From this observation, we propose that Au interlayer plays the unexpected role of a “buffer layer”, which dynamically functions as a medium for Li redistribution by propagating alloying reactions.Given the proposed new role of the interlayer, we expected the Li-metal deposition behavior to critically depend on the thermodynamic and kinetic properties of the interlayer metal and its alloying nature with Li. Si and Ag were chosen in this study, considering the availability of various alloys and the appreciable Li diffusivities in their alloys. When Si layer is applied (Figure 2a), the color changed during the early stages as gold, but subsequent behavior was noticeably different from that of the Au; Li metal preferentially precipitates at only a few sites, and whisker-shaped Li metal rapidly grows at these sites. On the other hand, in Ag interlayer (Figure 2b), the alloying reaction occurs first, followed by the uniform formation of numerous small nuclei. Interestingly, the two reactions occur nearly simultaneously, implying that both the alloying reaction and precipitation in the alloy are so fast that the sequential processes are unable to be distinguished. Regarding on this, the metal interlayers can be regarded as seed matrix for lithium precipitation.Further, Ag interlayer is more reversible upon Li stripping than Au or Si. The better efficacy of the lithium deposition/stripping process with Ag interlayer was further validated by comparative electrochemical testing of two electrode cells constructed with ‘100-nm-thick metal layer│LLZO │Li’ configuration. The results show that the coulombic efficiencies of cells using the various interlayers are closely related to the Li deposition and stripping behavior. The cell with Ag layer, which induces the most-uniform and reversible Li deposition among the tested metals, exhibits the highest efficiency of 71%, while that with Si layer shows 28%. Thus, it indicates that the interlayer can significantly affect the electrochemical performance of anode-free SSBs that employ solid electrolytes by regulating lithiation and de-lithiation behavior at the interface.Considering the ease of interlayer deposition on the LLZO surface and its wide applicability, we expect that our findings will provide useful guidelines for securing optimal interfaces for SSBs.REFERENCES[1] Aguesse, F.; Manalastas, W.; Buannic, L.; Lopez del Amo, J. M.; Singh, G.; Llordés, A.; Kilner, J., ACS Applied Materials & Interfaces 9, 3808-3816. (2017) Figure 1

Influence of the failure effect of MEMS capacitive high g acceleration sensor on the limit range and sensitivity

With the development of MEMS capacitive accelera-tion sensor to a higher measurement range (tens of thousands of g or even hundreds of thousands of g), the failure of the device microstructure under extreme mechanical impact has become a key factor restricting its performance improvement. Existing research mainly focuses on material stress failure and device structure optimization. Aiming at the failure of micro structure under impact, a simulation model of impact response of micro structure is established in this paper. Based on the existing over stress failure and device structure optimization, the stress failure effect and short-circuit failure effect of MEMS capacitive acceleration sensor under strong impact are proposed, and the influence rules of the two failure mechanisms on the sensor limit range and sensitivity are obtained. At the same time, the optimization design of the key structural parameters of the sensor is discussed.

Gate-damage accumulation and off-line recovery in SiC power MOSFETs with soft short-circuit failure mode

This paper proposes the detailed analysis of the short-circuit failure mechanism of a particular class of silicon carbide (SiC) power MOSFETs, exhibiting a safe fail-to-open-circuit type signature. The results are based on extensive experimental testing, including both functional and structural characterisation of the transistors, specifically devised to bring along gradual degradation and progressive damage accumulation. It is shown that the soft failure feature is associated with degradation and eventual partial shorting of the gate-source structure. Moreover, partial recovery, induced here by ad-hoc off-line biasing, is observed on degraded components. The results indicate that it is a realistic new option for deployment in the application to yield enhanced system level robustness and system-level hopping-home operational mode capability, of great importance in a number of reliability critical domains, such as, for instance, transportation.

Tin Whisker Growth on Electronic Assemblies Soldered with Bi-Containing, Pb-Free Alloys

With the introduction of environmental legislation, lead (Pb)-free materials have made their way into the electronics supply chain. As a result, tin whiskers may initiate and grow under specific conditions. Sufficiently long whiskers may cause in-field short circuit failures, which are a serious concern in many high-reliability applications such as aerospace, automotive, and medical. There are efforts in developing third generation Pb-free solder alloys to replace tin-silver-copper (Sn-Ag-Cu, or SAC). Bismuth (Bi) has been considered for inclusion in SAC alloys to reduce melting point and improve reliability. In this study, we examine whisker formation on small outline transistor (SOT) components assembled with SAC-Bi alloys after ambient temperature (25°C) or high temperature (85°C), high humidity (85% RH) storage. Four alloys were considered—Senju M42 (Sn-2.0Ag-0.7Cu-3.0Bi), Violet (Sn-2.25Ag-0.5Cu-6.0Bi), Sunflower (Sn-0.7Cu-7.0Bi), and SAC305 (Sn-3.0Ag-0.5Cu). The assemblies were finished with immersion tin (ImmSn) or electroless nickel immersion gold (ENIG), and some were intentionally contaminated prior to exposure. It was found that SAC305 tended to grow longer whiskers than SAC-Bi alloys, though more whiskers were found on the latter. Particle Stimulated Nucleation (PSN) of recrystallization of the β-Sn matrix, influenced by Bi precipitation, appears to influence dynamic recrystallization (DRX), the mechanism for whisker growth.

Understanding Short-Circuit Failure Mechanism of Double-Trench SiC Power MOSFETs

The short-circuit (SC) failure mechanism of double-trench silicon carbide (SiC) power metal-oxide- semiconductor field-effect transistors (MOSFETs) is comprehensively studied and analyzed. Unlike traditional planar-gate devices which die from thermal runaway, the double-trench ones exhibit a different SC failure phenomenon. After enduring an ultimate SC stress cycle, the gate of the double-trench device breaks down while the conducting and blocking characteristics of the body diode remain stable. During the SC process, a substantial negative gate current from the semiconductor side to the poly gate side is observed. Silvaco TCAD simulations demonstrate that ultrahigh current density and impact ionization appear at the gate trench corners simultaneously, driving the generated hot holes through the oxide, forming the negative gate current. The sustained action of this gate current component on the oxide finally results in the failure. Moreover, the influence that bias voltages have on the SC endurance capability of the device is analyzed. In general, the higher the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> are the shorter the SC endurance time will be. It is also found that the double-trench device fails with a higher junction temperature when stressed under a lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> condition, implying that the temperature rarely affects the failure, proving the correctness of the proposed SC failure mechanism.

Investigations of SiC MOSFET Short-Circuit Failure Mechanisms Using Electrical, Thermal, and Mechanical Stress Analyses

In this study, unique short-circuit failure mechanisms in 1.2-kV SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) at 400 and 800-V dc bias were investigated using experiments and numerical TCAD simulations, taking electrical, thermal, and mechanical stress into account. It was found that the fracture of the interlayer dielectric, caused by high mechanical stress due to different thermal expansion rates, is the source of failure in the 400-V short-circuit transient. The activation of the parasitic bipolar junction transistor under extreme high temperature was confirmed to be the failure mechanism in the 800-V short-circuit transient.

Failure Analysis of Computer Backplane Burning Down

The bottom plate burned out during the computer power-on detection process. This was analyzed. Firstly, the fault tree of the bottom plate was built and analyzed. Then a fault tree is established for the problem of capacitor short-circuit failure, and finally the possibility of capacitor problem is eliminated. After analysis, it is concluded that the cause of the burning of the bottom plate is the presence of foreign objects in the chassis. In the process of random vibration, foreign objects may be short-circuited to the power supply, resulting in a short circuit of the bottom plate, which may cause burnout. The power supply has an overcurrent protection mechanism, but the protection mechanism is that the power supply reduces the voltage output in the event of an overcurrent, so even if a short circuit occurs, the power supply will still output current, resulting in a burnout failure.

Assessment of operation of safety channel signal cables at nuclear power plants under fire conditions

Introduction. Signal cables of safety systems, installed at nuclear power plants (NPPs), retain the ability to conduct modulated signals during the time period needed to switch the reactor facility to a safe mode. However, the ability of signal cables to transmit signals correctly in the high temperature gas medium, which is typical for the early stage of a room fi re, has not been exposed to research.Aims and objectives. The co-authors offer a theoretical assessment of the ability of NPP safety system cables to correctly transmit modulated electric signals if exposed to fi re and current loads. The theoretical research into the temperature of the conductor of a signal cable at the initial stage of fi re has been performed towards this end.Theoretical background. The steady state heat conduction equation, describing heat transmission from the cable core to the environment through the cylinder-shaped insulation layer, is used to measure the temperature of the cable strand.Results and discussion. Temperature dependences describing the relation between the temperature of the conductor of a single - strand and single-wire cable KNEPng(А)-HF on the gas medium temperature are obtained. Relations between the temperature of the gas medium in the room on fi re and the current intensity in the electric cable (if the cable is laid vertically) are presented with account taken of the dependence between the specifi c resistance of the wire and the temperature if the maximal permissible operating temperature of cable strands is 70 °С, the maximal permissible operating temperature of cable strands in the overload operation mode is 80 °С, and the maximal cable strand heating temperature is equal to 160 °С when the short-circuit failure occurs. Maximal current intensity values are obtained for various operating modes in the condition of temperatures typical for the initial stage of an indoor fire, they allow to correctly conduct modulated signals within the time period needed to switch the reactor facility to a safe mode.Conclusions. The developed mathematical model and results of numerical experiments allow to assess the infl uence of the temperature in the room of a nuclear power plant in case of fi re on the ability of a signal cable of the safety system to transfer undistorted modulated signals depending on current loads and signal cable laying patterns (whether it is laid vertically or horizontally), and also to expand the range of the room temperature dependence on the current load provided in Electrical Installations Code (EIC).

Research on the Multiphysics Field-Circuit Coupling Model of Press Pack IGBT Considering the Application of Hybrid HVDC Breakers

Press pack insulated gate bipolar transistor (PP IGBT) is suitable for the hybrid high voltage direct current (HVdc) breaker to clear the fault current of the flexible HVdc transmission system with its advantages of double-side cooling, short-circuit failure mode, and easy to connect in series. However, it should have the ability to transmit the fault current, which is up to five or six times of its rated current, within several milliseconds depending on the distances between two stations without external cooling system. The junction temperature of PP IGBT will increase sharply and it is not possible to be measured during that situation. Therefore, the accurate prediction of junction temperature is extremely important for the packaging design of PP IGBT according to its working condition. In this article, an electro-thermo-mechanical multiphysics field-circuit coupling model of PP IGBT, which is coupled with the electrical, thermal, and mechanical fields, is proposed to predict the collector current, clamping force, and junction temperature. The 3-D mechanical model is decoupled with the 1-D electro-thermal Cauer network model to simplify this multiphysics model without reducing its accuracy. Both the normal and worst working conditions are analyzed through this multiphysics field-circuit model.

Experimental study on the dynamic behavior of prismatic lithium-ion battery upon repeated impact

The daily use of electric vehicles may cause mechanical loading on their batteries, either from one-time impact or repeated/accumulated impact from vibrations, curbstone impact, or minor contacts/scratches. Such repeated impact may ultimately lead to short-circuit failure of the batteries. Open literature comprehensively discusses the one-time impact, but a gap remains regarding battery safety behaviors in repeated impact cases. Therefore, in this study, the dynamic behavior of prismatic lithium-ion battery (PLIB) under repeated impact is experimentally investigated for the first time. The relationships between battery failure of short circuit with impact velocity, impact energy and impact times are revealed. The quantitative relationship between battery failure and indentation depth is constructed. Results show that the increase of impact velocity and energy significantly decreases the number of short-circuit impact. For the prismatic lithium-ion battery studied in this work, under the drop-weight impact test with 34.6 kg weight and 25 mm diameter of the hemispherical impact indenter, once the impact velocity reaches more than 1.75 and 4.0 m/s, the soft and hard short circuits are triggered, respectively. When the impact speed is less than the corresponding velocity, the battery failure of soft and hard short circuits can occur only after multiple impacts. Results provide new insights for understanding battery failure behaviors upon repeated impact and important guidance for battery design.

Optimizing a redundancy allocation problem with open-circuit and short-circuit failure modes at the component and subsystem levels

In failure-prone systems, it is important to take into considerations all the failure modes of each component to achieve the optimal system reliability. In this paper, a new series-parallel redundancy allocation problem is presented for a system in which the subsystems and components are subject to two different independent failure modes: short-circuit and open-circuit. It is assumed when a pre-determined number of a subsystem's components fail due to short- or open-circuit failure types, the subsystem fails. Moreover, when more than a pre-determined number of the system's subsystems fail due to short- or open-circuit failure types, the system fails. A new method based on the universal generating function is used to calculate the system's short-circuit failure probability, and the results are validated with the Monte-Carlo simulation. Then, a mathematical model for the considered RAP is presented to maximize the system's reliability. Finally, the proposed model is solved using a genetic algorithm.