Investigation on Short-Circuit Characterization and Optimization of 3.3-kV SiC MOSFETs

Abstract

The short-circuit (SC) ruggedness of 3.3-kV silicon carbide (SiC) MOSFETs is of great importance for traction applications. In this article, the SC characterization and failure mechanism of 3.3-kV planar-gate SiC MOSFETs are systematically studied by experiments and simulations. The measured SC withstanding time (SCWT) of 3.3-kV SiC MOSFETs is about 17 μs, and the SC energy density is 15.5 J/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Research demonstrates that the current clamping phenomenon is attributed to the high density of interface traps (Dit) in the gate oxide of 3.3-kV SiC MOSFETs. Furthermore, the positive temperature feedback mechanism and the triggering of parasitic n-p-n transistor are proved to cause the SC failure. At last, three optimized cell structures are proposed for improving the SC capability of 3.3-kV SiC MOSFETs, where the optimal SCWT is enhanced by 23% without degrading the forward conduction capability.