Short-channel Transistors Research Articles

First-Principles Investigation of Janus MgZnXY (X, Y = O, S, Se, Te; X ≠ Y) Monolayers for Short-Channel Field Effect Transistor

First-Principles Investigation of Janus MgZnXY (X, Y = O, S, Se, Te; X ≠ Y) Monolayers for Short-Channel Field Effect Transistor

Phase-Change Stamp with Highly Switchable Adhesion and Stiffness for Damage-Free Multiscale Transfer Printing.

Transfer printing is a technology widely used in the production of flexible electronics and vertically stacked devices, which involves the transfer of predefined electronic components from a rigid donor substrate to a receiver substrate with a stamp, potentially avoiding the limitations associated with lithographic processes. However, the stamps typically used in transfer printing have several limitations related to unwanted organic solvents, substantial loading, film damage, and inadequate adhesion switching ratios. This study introduces a thermally responsive phase-change stamp for efficient and damage-free transfer printing inspired by the adhesion properties observed during water freezing and ice melting. The stamp employs phase-change composites and simple fabrication protocols, providing robust initial adhesion strength and switchability. The underlying mechanism of switchable adhesion is investigated through experimental and numerical studies. Notably, the stamp eliminates the need for extra preload by spontaneously interlocking with the ink through in situ melting and crystallization. This minimizes ink damage and wrinkle formation during pickup while maintaining strong initial adhesion. During printing, the stamp exhibits a sufficiently weak adhesion state for reliable and consistent release, enabling multiscale, conformal, and damage-free transfer printing, ranging from nano- to wafer-scale. The fabrication of nanoscale short-channel transistors, epidermal electrodes, and human-machine interfaces highlights the potential of this technique in various emerging applications of nanoelectronics, nano optoelectronics, and soft bioelectronics.

High-Yield Production of High-κ/Metal Gate Nanopattern Array for 2D Devices via Oxidation-Assisted Etching Approach.

2D materials with atomically thin nature are promising to develop scaled transistors and enable the extreme miniaturization of electronic components. However, batch manufacturing of top-gate 2D transistors remains a challenge since gate dielectrics or gate electrodes transferred from 2D material easily peel away as gate pitch decreases to the nanometer scale during lift-off processes. In this study, an oxidation-assisted etching technique is developed for batch manufacturing of nanopatterned high-κ/metal gate (HKMG) stacks on 2D materials. This strategy produces nano-pitch self-oxidized Al2O3/Al patterns with a resolution of 150nm on 2D channel material, including graphene, MoS2, and WS2 without introducing any additional damage. Through a gate-first technology in which the Al2O3/Al gate stacks are used as a mask for the formation of source and drain, a short-channel HKMG MoS2 transistor with a nearly ideal subthreshold swing (SS) of 61mVdec-1, and HKMG graphene transistor with a cut-off frequency of 150GHz are achieved. Moreover, both graphene and MoS2 HKMG transistor arrays exhibit high uniformity. The study may bring the potential for the massive production of large-scale integrated circuits using 2D materials.

A Quasi-Ballistic Model for Short Channel Monolayer Graphene Field Effect Transistor Including Scattering Effects

In this work, the Landauer approach-based short channel model of a graphene field effect transistor has been presented. The quasi-ballistic and ballistic transport mechanism is explained by this approach for nanoscale transistors. The concept of the virtual source is considered to obtain the carrier density in active regions. Here, we apply the Landauer approach for short-channel graphene field effect transistors relating to the parameter in the virtual source model. The mobility of the model has been improved including various scattering effects like impurity scattering, acoustic phonon scattering, and optical phonon scattering. The dynamic resistance model is considered due to asymmetry transport in the electron branch and hole branch. The proposed model has been verified with several experimental works for model validation. The comparisons of the model simulation with several experimental results that have been reported in the literature match well for different short channel lengths of graphene.

Enhancing Reliability of Short-Channel Dual Gate InGaZnO Thin Film Transistors by Bottom-Gate Oxide Engineering

Enhancing Reliability of Short-Channel Dual Gate InGaZnO Thin Film Transistors by Bottom-Gate Oxide Engineering

High-performance nano-scale InSnO transistors

Nanoscale short-channel oxide thin film transistors (TFTs) have attracted widespread research interest due to their potential applications in advanced display and memory devices. In this work, we fabricate 10 μm channel length indium-tin-oxide (ITO) TFTs and analyze the uniformity and repeatability of ITO TFTs at the long channel range. Then we fabricate ITO TFTs with a series of channel lengths ranging from 10 μm to 150 nm and through an optimized process we finally fabricate 130 nm channel length high-performance ITO TFTs with an on-state current of 93 (μA/μm), a subthreshold swing of 102 (mV decade–1), and on/off ratio over 107 at a drain voltage of 3 V.

Dopant-mediated carrier tunneling in short-channel two-dimensional transistors

Electronic effects of dopant atoms in short-channel 2D transistors have been unraveled by quantum transport simulation, featuring channel length-dependent functionalities of assisted tunneling and charge scattering.

Analog CMOS Design in Nanometer Regime

There is no doubt that the short-channel effects have affected the analysis and design of modern analog CMOS integrated circuits significantly. Thus, models that take into account these effects must be adopted in order to obtain more accurate results. In this paper, the AC small-signal low-frequency equivalent circuit of the short-channel MOSFET transistor is developed using an appropriate model. The impact of short-channel effects on the operation of basic building blocks of analog integrated circuits such as basic amplifier configurations, cascode stage, differential amplifier and composite transistor is investigated quantitatively. Additionally, the nonlinear distortion is investigated using the adopted model.

Ultrafast Magnesium Reaction-Induced Source/Drain for Short-Channel Top-Gate Self-Aligned Oxide Thin-Film Transistors

Ultrafast Magnesium Reaction-Induced Source/Drain for Short-Channel Top-Gate Self-Aligned Oxide Thin-Film Transistors

Multimodal force and temperature tactile sensor based on a short-channel organic transistor with high sensitivity

In this manuscript, we report on a novel architecture for the fabrication of highly sensitive multimodal tactile transducers, for the simultaneous detection of temperature and force. Such devices are based on a flexible Organic Charge Modulated Field Effect Transistor (OCMFET) coupled with a pyro/piezoelectric element, namely a commercial film of poly-vinylene difluoride (PVDF). The reduction of the channel length, obtained by employing a low-resolution vertical channel architecture, allowed to maximize the ratio between the sensing area and the transistor’s channel area, a technological approach that allows to considerably enhance both temperature and force sensitivity, while at the same time minimize the sensor’s dimensions. Thanks to the employment of a straightforward, up-scalable, and highly reproducible fabrication process, this solution represents an interesting alternative for all those applications requiring high-density, high-sensitivity sensors such as robotics and biomedical applications.

Edge Contacts to Atomically Precise Graphene Nanoribbons.

Bottom-up-synthesized graphene nanoribbons (GNRs) are an emerging class of designer quantum materials that possess superior properties, including atomically controlled uniformity and chemically tunable electronic properties. GNR-based devices are promising candidates for next-generation electronic, spintronic, and thermoelectric applications. However, due to their extremely small size, making electrical contact with GNRs remains a major challenge. Currently, the most commonly used methods are top metallic electrodes and bottom graphene electrodes, but for both, the contact resistance is expected to scale with overlap area. Here, we develop metallic edge contacts to contact nine-atom-wide armchair GNRs (9-AGNRs) after encapsulation in hexagonal boron-nitride (h-BN), resulting in ultrashort contact lengths. We find that charge transport in our devices occurs via two different mechanisms: at low temperatures (9 K), charges flow through single GNRs, resulting in quantum dot (QD) behavior with well-defined Coulomb diamonds (CDs), with addition energies in the range of 16 to 400 meV. For temperatures above 100 K, a combination of temperature-activated hopping and polaron-assisted tunneling takes over, with charges being able to flow through a network of 9-AGNRs across distances significantly exceeding the length of individual GNRs. At room temperature, our short-channel field-effect transistor devices exhibit on/off ratios as high as 3 × 105 with on-state current up to 50 nA at 0.2 V. Moreover, we find that the contact performance of our edge-contact devices is comparable to that of top/bottom contact geometries but with a significantly reduced footprint. Overall, our work demonstrates that 9-AGNRs can be contacted at their ends in ultra-short-channel FET devices while being encapsulated in h-BN.

Compact Modeling of Process Variations in Nanosheet Complementary FET (CFET) and Circuit Performance Predictions

In this work, a semi-analytical compact model of random process fluctuations in nanosheet (NS) gate-all-around (GAA) complementary FET (CFET) is proposed, including work-function variation (WFV), line edge roughness (LER), and gate edge roughness (GER). Different from the conventional NS GAA FET, GER has a significantly different impact on NS GAA CFET, due to the additional p-type work-function (p-WF) liner for p-FET threshold voltage tuning as well as the common metal gate, and a negative correlation with p-WF thickness is introduced into GER model. The proposed model is embedded into Berkeley short-channel insulated-gate field-effect transistor model-common multi-gate (BSIM-CMG) to predict the device performance variability by HSPICE Monte Carlo (MC) simulations. Excellent agreement between stochastic TCAD and HSPICE MC simulations is demonstrated. The effect of process variations on the power-performance-area (PPA) of standard cells (SDCs) and ring oscillator (RO) circuit is predicted by the proposed model. Most of the process variations make a more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 10% to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 20% change in power consumption in NOR2. WFV has the greatest impact on RO PPA, making a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 10% to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 12.3% change in power consumption. The proposed model provides a helpful guideline for the random variation-aware CFET circuit design and related technology process development.

A W-Band Vector Modulator Using Short-Channel Transistor Current Sources and Impedance Compensation Varactors

A W-band vector modulator based on vector summing with a Gilbert-cell is presented, in which two kinds of error-reducing schemes are applied to the summing circuit. One is to use current sources made of short channel transistors to take advantage of the channel length modulation effect. The other is to introduce impedance correction varactors at the input. It controls both gain and phase by using a digital-to-analog converter (DAC) which is designed to make the output impedance of the summing circuit constant regardless of states. The intrinsic gain and phase errors are also analyzed with the help of a simple current model of a MOS transistor, which explains the error-reducing schemes. It was implemented in 28-nm CMOS technology, which consumes only 7.7mA of DC and occupies an area of 0.11mm2 (excluding pads). The RMS gain error of 0.1dB and the RMS phase error of 1.3° were measured with 4-bit gain and 6-bit phase controls at 94 GHz, where the gain dynamic range was around 15 dB.

Prediction of Semiconducting 2D Nanofilms of Janus WSi2P2As2 for Applications in Sub-5 nm Field-Effect Transistors

Searching for eligible two-dimensional (2D) semiconductors to fabricate high-performance (HP) short-channel field-effect transistors (FETs) at the nanoscale is essential toward the continuous miniaturization of devices. Herein, we predict the 2D Janus WSi2P2As2 semiconductor and propose it as a qualified channel material for sub-5 nm FETs by using first-principles calculations. The results demonstrate that the monolayer Janus WSi2P2As2 is a 2D semiconducting nanofilm with a band gap of 0.83 eV, a hole mobility of 490 cm2 V–1 s–1 in the armchair direction, and an out-of-plane polarization. Benefiting from these outstanding intrinsic characteristics, the performance of the 5 and 3 nm gate-length WSi2P2As2 FETs can fulfill the International Technology Roadmap for Semiconductors for HP standards after employing optimizing strategies, including underlap structure, dielectric project, and cold source. Our results promote the development of new 2D nanomaterials and device architectures for designing HP short-channel FETs.

Ultrashort channel chemical vapor deposited bilayer WS2 field-effect transistors

Two-dimensional transition metal dichalcogenides (TMDs) are potential candidates for next generation channel materials owing to their atomically thin structure and high carrier mobility, which allow for the ultimate scaling of nanoelectronics. However, TMDs-based field-effect transistors are still far from delivering the expected performance, which is mainly attributed to their high contact resistance and low saturation velocity (vsat). In this work, we report high-performance short-channel WS2 transistors based on bandgap engineering. The bilayer WS2 channel not only shows a higher average field-effect mobility (μFE) than the monolayer channel but also exhibits excellent metal-Ohmic contact using a regular physical vapor deposition deposited Ni/Au contact, reducing the Rc value to a record low value of 0.38 kΩ · μm without any intentional doping. The bilayer WS2 device of the 80 nm channel exhibits a high on-state current of 346 μA/μm at Vds = 1 V, near-zero drain-induced barrier lowering, and a record high Ion/Ioff ratio over 109. Furthermore, a record high on-state current of 635 μA/μm at Vds = 1 V and a record high vsat of 3.8 × 106 cm/s have been achieved for a shorter 18 nm channel device, much higher than previous WS2 transistors. This work reveals the intrinsically robust nature of bilayer WS2 crystals with promising potential for integration with conventional fabrication processes.

Approaching the quantum limit in two-dimensional semiconductor contacts.

The development of next-generation electronics requires scaling of channel material thickness down to the two-dimensional limit while maintaining ultralow contact resistance1,2. Transition-metal dichalcogenides can sustain transistor scaling to the end of roadmap, but despite a myriad of efforts, the device performance remains contact-limited3-12. In particular, the contact resistance has not surpassed that of covalently bonded metal-semiconductor junctions owing to the intrinsic van der Waals gap, and the best contact technologies are facing stability issues3,7. Here we push the electrical contact of monolayer molybdenum disulfide close to the quantum limit by hybridization of energy bands with semi-metallic antimony ([Formula: see text]) through strong van der Waals interactions. The contacts exhibit a low contact resistance of 42 ohm micrometres and excellent stability at 125 degrees Celsius. Owing to improved contacts, short-channel molybdenum disulfide transistors show current saturation under one-volt drain bias with an on-state current of 1.23 milliamperes per micrometre, an on/off ratio over 108 and an intrinsic delay of 74 femtoseconds. These performances outperformed equivalent silicon complementary metal-oxide-semiconductor technologies and satisfied the 2028 roadmap target. We further fabricate large-area device arrays and demonstrate lowvariability in contact resistance, threshold voltage, subthreshold swing, on/off ratio, on-state current and transconductance13. The excellent electrical performance, stability and variability make antimony ([Formula: see text]) a promising contact technology for transition-metal-dichalcogenide-based electronics beyond silicon.

High-stability flexible radio frequency transistor and mixer based on ultrathin indium tin oxide channel

In this work, a high-performance flexible radio frequency transistor using an ultrathin indium tin oxide film channel based on a solution-cast thin polyimide substrate has been demonstrated. The 60 nm short channel transistor shows a record high cut-off frequency of 5 GHz and a maximum oscillation frequency of 11 GHz with high uniformity among 40 devices. The radio frequency characteristics under various bending conditions have been systematically studied under a bending radius of 5 mm for 10 000 times and a bending radius of 1 mm for 1000 times, showing excellent stability with only 20% decrease in the cut-off frequency. Furthermore, a flexible frequency mixer has also been demonstrated at 2.4 GHz with decent conversion gains.

High-κ perovskite membranes as insulators for two-dimensional transistors.

The scaling of silicon metal-oxide-semiconductor field-effect transistors has followed Moore's law for decades, but the physical thinning of silicon at sub-ten-nanometre technology nodes introduces issues such as leakage currents1. Two-dimensional (2D) layered semiconductors, with an atomic thickness that allows superior gate-field penetration, are of interest as channel materials for future transistors2,3. However, the integration of high-dielectric-constant (κ) materials with 2D materials, while scaling their capacitance equivalent thickness (CET), has proved challenging. Here we explore transferrable ultrahigh-κ single-crystalline perovskite strontium-titanium-oxide membranes as a gate dielectric for 2D field-effect transistors. Our perovskite membranes exhibit a desirable sub-one-nanometre CET with a low leakage current (less than 10-2 amperes per square centimetre at 2.5 megavolts per centimetre). We find that the van der Waals gap between strontium-titanium-oxidedielectricsand 2D semiconductors mitigates the unfavourable fringing-induced barrier-lowering effect resulting from the use of ultrahigh-κ dielectrics4. Typical short-channel transistors made of scalable molybdenum-disulfidefilms by chemical vapour deposition and strontium-titanium-oxide dielectrics exhibit steep subthreshold swings down to about 70 millivolts per decade and on/off current ratios up to 107, which matches the low-power specifications suggested by the latest International Roadmap for Devices and Systems5.

DC response, low-frequency noise, and TID-induced mechanisms in 16-nm FinFETs for high-energy physics experiments

Total-ionizing-dose (TID) mechanisms are evaluated in 16 nm Si bulk FinFETs at doses up to 1 Grad(SiO2) for applications in high-energy physics experiments. The TID effects are evaluated through DC and low-frequency noise measurements by varying irradiation bias conditions, transistor channel lengths, and fin/finger layouts. The TID response of nFinFETs irradiated under positive gate bias at ultrahigh doses shows a rebound of threshold voltage with significant increase in the 1/f noise amplitude. The degradation is related to the generation of border and interface traps at the upper corners of STI oxides and at the gate oxide/channel interfaces. In contrast, pFinFETs have the worst degradation due to positive charge trapping in STI oxides, which severely degrades the device transconductance and total drain current, while negligible effects are visible in the threshold voltage and 1/f noise. The TID sensitivity depends strongly on the transistor layout. Short-channel devices have the best TID tolerance thanks to the influence of halo implantations, while pFinFETs designed with low number of fins have the worst degradation because of high densities of positive charge in the surrounding thick STI oxides. As a guideline for IC design, short-channel transistors with more than 4-fins may be preferred in order to facilitate circuit qualification.

High-performance monolayer or bilayer SiC short channel transistors with metallic 1T-phase MoS2 contact

In this paper, high-performance monolayer or bilayer SiC short channel transistors with metallic 1T-Phase MoS2 contact have been proposed and investigated by using ab initio simulations. The results show that monolayer or bilayer SiC Schottky-barrier field-effect transistors (SBFET) could conquer the short channel effect, even if the channel length is reduced to 4.1 nm. The p-type ON-currents of monolayer SiC-SBFET, bilayer AB-stacked SiC-SBFET, and bilayer AA-stacked SiC-SBFET are 1132 μA/μm, 980 μA/μm, and 1457 μA/μm, respectively. The all could satisfy the requirement of the high-performance transistor outlined by International Technology Roadmap for Semiconductors (ITRS, 2013 version) for production year 2028. However, the n-type ON-currents of above SiC-SBFETs are 35 μA/μm, 21 μA/μm, and 229 μA/μm, which are much lower than that of p-type ON-currents. Comparing spectral current and spatial local density of states are used to explore the great differences between the p-type and n-type ON-currents.