Short-channel NMOS Devices Research Articles

An Accurate Method for Extracting the Critical Field in Short Channel NMOS Devices

In this letter, an accurate method for extracting the critical fieldEcin short channel MOSFET's is presented. The principle of this method is based on the comparison between two models which give drain saturation voltage evolution against gate voltageVdsat(Vg)continuously. The results obtained by this technique have shown better agreement with measurements data and have allow in the same time to determine the validity domain of Sodini's law [1].

SPICE models for flicker noise in n-MOSFETs from subthreshold to strong inversion

The two main sources of low-frequency flicker noise are mobility fluctuations and number fluctuations. Our experiments on NMOS noise measurements were done from subthreshold to saturation region of operation for both long-channel (5 /spl mu/m) and short-channel (as small as 0.6 /spl mu/m) NMOS transistors. The results suggest that for both types that in the saturation region, the flicker noise is due to the surface state effect and the noise equations, NLEV=2 and 3, in SPICE, HSPICE, and PSPICE are most appropriate. For short-channel devices, due to the effects of velocity saturation and the resulting nonlinear transconductance (g/sub m/) variation with gate bias voltage, the input-referred voltage noise increases as the gate-source voltage increases instead of staying constant as it does for long-channel devices. In the subthreshold region, the input-referred voltage noise decreases drastically as the gate-source voltage increases for both long-channel and short-channel NMOS devices. Simulations have been done using PSPICE and HSPICE, with noise level (NLEV)=3 and device model level 3 and BSIM 3.2 and 3.3. The results from PSPICE version 8.0 level 7 (BSIM 3.3) and SPICE level 3 compare favorably with the measured noise phenomena for the short-channel and long-channel NMOS devices, respectively.

The inversion layer of subhalf-micrometer n- and p-channel MOSFET's in the temperature range 208-403 K

Minority carrier mobility has been extracted from I-V measurements on N- and PMOS-transistors entirely processed by means of X-ray lithography with effective channel lengths down to 0.35 mu m. The measurements have been performed within the temperature range 208-403 K (-65 degrees C to +130 degrees C). The accuracy of the mobility determination has been investigated, especially with regard to the determination of the effective channel length and the series resistance. The results indicate a significant mobility reduction for short-channel NMOS devices at temperatures below 300 K. A slight increase of the threshold-voltage is observed in the short-channel region. Both effects can be required by an inhomogeneous lateral doping profile within the channel due to standard submicron technology; this has been confirmed by two-dimensional device simulation. >

DIBL in short-channel NMOS devices at 77 K

Detailed experimental and two-dimensional numerical simulation results on drain-induced barrier lowering (DIBL) versus channel length at 300 and 77 K in short-channel NMOS devices are presented. It is found that by decreasing the temperature from 300 to 77 K. DIBL in NMOS devices with effective channel lengths (L) from 0.5 to 2.0 mu m is improved for the range of L 1.2 mu m, but is worse for L between 0.6 and 1.2 mu m. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, which includes device modeling at cryogenic temperatures, was used to investigate this unique characteristic. The measured DIBL characteristics can be explained physically as the transition from surface DIBL through the subsurface DIBL to the bulk DIBL or punchthrough effect at 300 K, but almost a surface DIBL for the whole range of channel length variation at 77 K. Design considerations for the channel doping profile for low-temperature operation based on keeping the same DIBL and V/sub TH/ as required for room-temperature operation are briefly discussed. >

Anomalous drain-induced barrier lowering in short channel NMOS devices at 77 K

Anomalous results on drain-induced barrier lowering (DIBL) in short channel NMOS devices at 77K are presented. It was found that for devices with channel lengths 0.7 and 1.3 μm, the DIBL measured by the change in gate voltage induced by a unit change in drain voltage at a fixed drain current was worse at 77K than at 300K. However, for devices that were either shorter than 0.7 μm or longer than 1.3 μm, DIBL was improved at 77K compared with 300K. The experimental results were in good agreement with the numerical calculations using MINIMOS 4.0.

The effect of impact ionization induced bipolar action on n-channel hot-electron degradation

The relationship between the total impact ionization rate and the measured substrate current is analyzed, using short-channel NMOS devices. It is shown that holes that are injected into the source and turn on the parasitic source-bulk-drain bipolar may actually be a significant portion of the total impact ionization current. The authors explain how the commonly used model, which ignores this bipolar effect, can lead to incorrect predictions regarding hot-electron degradation. A related criterion for maximum source-drain voltage during accelerated stress is discussed and justified. >