Short-channel MOS Devices Research Articles

A two-dimensional analytical-model-based comparative threshold performance analysis of SOI-SON MOSFETs

A generalized threshold voltage model based on two-dimensional Poisson analysis has been developed for SOI/SON MOSFETs. Different short channel field effects, such as fringing fields, junction-induced lateral fields and substrate fields, are carefully investigated, and the related drain-induced barrier-lowering effects are incorporated in the analytical threshold voltage model. Through analytical model-based simulation, the threshold voltage roll-off and subthreshold slope for both structures are compared for different operational and structural parameter variations. Results of analytical simulation are compared with the results of the ATLAS 2D physics-based simulator for verification of the analytical model. The performance of an SON MOSFET is found to be significantly different from a conventional SOI MOSFET. The short channel effects are found to be reduced in an SON, thereby resulting in a lower threshold voltage roll-off and a smaller subthreshold slope. This type of analysis is quite useful to figure out the performance improvement of SON over SOI structures for next generation short channel MOS devices.

A Low-Power Ultrawideband CMOS Power Detector With an Embedded Amplifier

A self-biased low-power CMOS power detector (PD) is proposed and demonstrated in this paper. The detector utilizes the nonlinear characteristics of short-channel MOS devices operating in either a saturation or subthreshold regime to generate a dc current that is proportional to the input RF signal power. The operating regimes of MOS devices depend on input RF power levels. A quasi-T-coil matching network providing 50- matching from 0.5 to 20 GHz is designed and analyzed. An embedded amplifier is added to enhance the sensitivity of the PD when the input power level is low. The circuit that is implemented in a 0.13- CMOS process occupies an active area of 0.085 . In the matched frequency range, the measured input dynamic range is 47 dB with an overall sensitivity of 26.8 mV/dB. The output dc voltage response is nearly frequency-independent in the linear operating range, varying by less than 1.9 dB for a given input RF power level, as the RF frequency is swept across the operating frequency range. With a standard 1.2-V supply, the static power consumption is about 0.1 mW, which decreases to with a 0.5-V supply, while the operating frequency remains unchanged.

Backscattering coefficient and drift-diffusion mobility extraction in short channel MOS devices

A new method for the extraction of the backscattering coefficient in nanoMOS devices has been demonstrated. The method, which relies on mobility measurements in linear operation, proves very simple and reliable for the determination of the ballistic rate of transport. Moreover, it allows to obtain the drift-diffusion mobility corrected from ballistic effects and therefore to make a diagnostic of the scattering mechanisms at small gate length.

Unified current equation for predictive modeling of submicron MOSFETs

For short-channel submicron MOS devices, we present a unified current equation, which covers both weak and strong inversion. The current in weak inversion is controlled by the subthreshold slope, for which we derive a new physics-based, predictive model. Furthermore, a new model for the carrier mobility is presented, which allows to derive closed-form current equations with good scalability. The approaches have been implemented in the compact model PREDICTMOS and are qualified by comparison with numerical device simulations and measurements.

New Method for Determination of Drain Saturation Voltage in Short Channel MOS Devices Between Liquid Helium to Room Temperature

A new method for drain saturation voltage extraction in submicron MOSFETs is presented. It is based on measurements of the partial derivative of the impact ionization rate. The method has been tested using main of channel length MOSFET devices and compared with others methods.

A New Approximate Model for Short-Channel MOS Devices

A New Approximate Model for Short-Channel MOS Devices

A New Approximate Model for Short-Channel MOS Devices

A new solution to the two-dimensional Poisson equation, based on real physical facts has been worked out. Thus it has been possible to construct an original and physically consequent approximate model of current-voltage characteristic for short-channel MOS devices. The expressions do not contain free parameters as long as one can neglect the degradation of the carrier mobility in the inversion layer. If we take this effect into consideration, the model mentioned above will have one free (fitting) parameter only.

A CMOS mismatch model and scaling effects

In this letter a novel single-pair mismatch model for short-channel MOS devices is developed, and scaling effects of mismatch distributions are investigated based on the model. The mismatch effect is modeled with threshold voltage, current factor, source resistance, and body factor mismatches. SPICE mismatch simulation is defined with mismatch parameters extracted from the model for accurate offset estimation in circuit simulation. Scaling effects with device size are investigated based on statistical mismatch data, and the results indicate that CMOS mismatch is induced by both local edge roughness and global variations. In addition, a /spl radic/n-law model is developed for modeling gate-finger dependence of mismatch.

Simple analytical model for short-channel MOS devices

A simple analytical model derived from a quasi-two-dimensional analysis with a nonvanishing E-field derivative at the pinchoff point and a continuous output conductance at the transition point for short-channel MOSFETs is presented. This model also covers mobility reduction, carrier velocity saturation, body, channel-length modulation, source-drain series resistance and short-channel effects for an accurate determination of the pinchoff point location without internal numerical iterations as compared to other models. This model can be used to describe the channel-length modulation effects more accurately in circuit simulation with short-channel MOSFETs.

Operation of short-channel depletion-mode MOS devices at liquid-nitrogen temperature

Experimental observations that depletion-mode MOS devices optimized for room temperature can also work well when immersed in liquid nitrogen are reported in which the classical impurity freeze-out effect seems to vanish on short-channel devices if the drain voltage is not too small. This is attributed to field-assisted ionization mechanisms such as the Poole-Frenkel effect, with possible enhancement by self-heating. The MINIMOS 4 device simulator was modified to introduce this effect and then to check the validity of this assumption by comparison with experimental results. To prove that it is possible to take advantage of this effect a 3-bit feedback adder, used as a benchmark circuit, has been processed in an enhancement-depletion 0.5- mu m NMOS technology optimized for room temperature wherein the cooling from 300 to 77 K results in an improvement from 1 to 1.3 GHz for the maximum clock frequency of operation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Substrate currents in short buried-channel PMOS devices at cryogenic temperatures

For MOSFETs biased in the saturation mode, measurable substrate current due to impact ionization near the drain often flows. If this substrate current is large enough, the substrate bias generator can become overloaded and breakdown can occur if the source - substrate junction is forward biased. Substrate currents can also be used as a reliability monitor of hot carrier effects in short channel MOS devices. In this paper, detailed experimental results are presented on the variation of peak substrate currents in short buried-channel PMOS devices from their I DS– V GS curves at varying substrate and drain biases, at temperatures between 77 and 300 K. From the experimental results, an empirical curve-fit model of the peak substrate current normalized to the drain current and for a constant drain bias was found to be / P,SUB// DS≈α(T, V BS)L -β(T, V BS) Numerical values for the functional dependence of α and β are determined. Detailed results on these functional dependences on temperature and bias voltages are reported.

A charge-based capacitance model of short-channel MOSFETs

A quasi-static two-dimensional intrinsic capacitance model for short-channel MOSFETs is discussed. It is derived based in a physically based charge-sharing scheme and implemented using a quasi-static solution of a MOS device simulator. Two-dimensional field-induced mobility degradation, velocity saturation, and short-channel effects are included in the model. The charge conservation rule holds, and channel charge partitioning is properly treated. The simulation results clearly show the importance of two-dimensional field-induced effects to short-channel MOS devices. Comparison of the simulated results with experimentally measured data shows that the model is far more reliable than the analytical one. The method can be used to link a device simulator and a circuit simulator for accurate timing calculation in both digital and analog MOS integrated circuits. >

An engineering model for short-channel MOS devices

An engineering model for short-channel MOS devices which includes the effect of carrier drift velocity saturation is described. Based on a piecewise carrier drift velocity model, simplified expressions for the DC drain current I/sub D/, the small signal transconductance g/sub m/ and the output conductance g/sub ds/ in the saturation region are derived. For a given gate voltage, the expressions depend only on the threshold voltage V/sub T/ and the dimensions of the device, whose desired values are normally known.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

MOSLAP???A Circuit Simulation Program for Teaching Short-Channel MOS Circuit Design

The current approach to teaching MOS circuit design is based on the classic square-law MOSFET device model. This model is capable of adequately modeling long-channel devices; however, current levels of technology are providing short-channel MOS devices which exhibit significant second-order effects which cannot be accounted for by the square-law model. Due to inherent increases in model complexity, the need arises for the use of computers to aid in designing MOS circuits containing short-channel devices. Presented here is MOSLAP (MOS loadline analysis program), a new interactive circuit simulation tool for teaching short-channel MOS circuit design. MOSLAP contains a complete short-channel MOSFET model, and is capable of analyzing general MOS circuits. MOSLAP can perform dc analysis, small-signal ac analysis, dc transfer function analysis, and can generate various loadlines for visual inspection of dc operating point information. This last feature makes MOSLAP unique.

Breakdown voltage characteristics of thin oxides and their correlation to defects in the oxide as observed by the EBIC technique

Thin oxides are widely used as the tunneling dielectric in floating gate EEPROM devices and as gate dielectric in short-channel MOS devices. The oxides are required to have high breakdown voltage and low defect density for reliable operation of the devices. With the Electron Beam Induced Current (EBIC) technique, defects in the oxide which lead to lower values of the oxide breakdown voltage have been observed.

Carrier mobility determination in short-channel MOS devices

The measurement of the effective carrier mobility in the inversion layer becomes complicated when the device dimentions are reduced. A method is described to determine the field effect mobility, the decrease of the mobility under the influence of normal electrical field, described by the surface scattering factor, and the drain and source series resistances. The degradation in the properties of the Si−SiO 2 region which is manifested as a decrease in the low field mobility of the inversion layer carriers is considered.

Threshold voltage in short-channel MOS devices

The threshold voltage in short-channel MOS transistors was investigated by use of a two-dimensional numerical solution of Poisson's equation and experimental measurements on devices of 5.15-, 3.15-, and 2.15-µm channel length. The assumption of constant equipotential surface in the oxide implicit in the charge-sharing technique is not valid in devices of shorter Channel lengths and at larger operating voltages. The numerical determination of the threshold voltage from the two-dimensional analysis agrees with experimental results. Unlike previous work, the charge-sharing model was investigated from an electric-field point of view. The inadequacies of the charge-sharing model are elucidated qualitatively and quantitatively.

Electrical characterization of the polycide sidewall profile

An electrical method for characterizing the polycide (i.e., silicide on top of poly-Si) side wall profile is presented. It is based on resistance and effective channel length measurements. The electrical character of the method makes it particularly applicable for process control of the polycide side wall profile, which critically determines the electrical characteristics of short channel MOS devices. Automation of measurements and evaluation is possible.

Hot-electron injection into the oxide in n-channel MOS devices

In recent years, interest in hot-electron injection current in MOS devices has increased due to advances in device concepts and technology. The injection current to the gate is the mechanism for programming FAMOS devices and determines the potential degradation of short-channel MOS devices due to electron trapping in the oxide. This work presents an accurate indirect current measurement technique based on charge transport to the floating gate in a FAMOS structure. The measurement bypasses effects of trapping and local heating, allowing full characterization of parameter, voltage, and temperature dependence down to gate current levels of 10-16A. Based on this characterization, a new qualitative model of hot-electron injection into the oxide is proposed. The basic assumption in the model is the spherical symmetry of the momentum distribution function of the hot electrons. This assumption leads to the experimentally observed dominant role of the lateral electric field in the pinchoff region in determining gate current behavior. The model provides an explanation of gate current parameter and voltage dependence, and suggests correlation between gate current and substrate impact ionization current in a range of operating voltages. This correlation is substantiated experimentally for a range of device parameters and voltages.

Characterization of Ion-Implanted SiO2 Properties Applicable to Laser Processing

ABSTRACTThe use of an antireflection oxide film applicable to laser annealing process has been investigated. The optical properties of the antireflection oxide film are changed by ion implantation although the antireflection characteristics are similar to calculations based on nominal optical constants. Implantation annealing can be achieved at powers lower than predicted by calculations. Using the antireflection(AR) technique, n+-p junction diodes were fabricated. Reverse bias junction leakage is around 10-9 A/cm2 , comparable to those annealed thermally. Short channel MOS devices were also fabricated and indicated much better resistance to the short channel effect than those thermally annealed.