Substrate currents in short buried-channel PMOS devices at cryogenic temperatures

Abstract

For MOSFETs biased in the saturation mode, measurable substrate current due to impact ionization near the drain often flows. If this substrate current is large enough, the substrate bias generator can become overloaded and breakdown can occur if the source - substrate junction is forward biased. Substrate currents can also be used as a reliability monitor of hot carrier effects in short channel MOS devices. In this paper, detailed experimental results are presented on the variation of peak substrate currents in short buried-channel PMOS devices from their I DS– V GS curves at varying substrate and drain biases, at temperatures between 77 and 300 K. From the experimental results, an empirical curve-fit model of the peak substrate current normalized to the drain current and for a constant drain bias was found to be / P,SUB// DS≈α(T, V BS)L -β(T, V BS) Numerical values for the functional dependence of α and β are determined. Detailed results on these functional dependences on temperature and bias voltages are reported.