Short Channel Mobility Research Articles

Vertically-stacked silicon nanosheet field effect transistors at 3 nm technology nodes - simulation at nanoscale

Feasibility of vertically-stacked silicon nanosheet FETs (SNS-FETs) for extreme scaling at 3 nm technology node are investigated for the first time as one of the possible solutions to continue to enhance the performances of the CMOS technology. In this work, we use 3D predictive simulations to study the performance potential of SNS-FETs at 3 nm technology node. With the end of happy scaling era, change of device architecture has raised integration complexity along with severe short channel effects, mobility degradation, variability and quantum tunnelling leakage. These are the major challenges as device dimensions are scaled for ultimate scaling below 7 nm. Towards low power and high speed (more-than-Moore applications), nanowires and nanosheet transistors are being proposed. Today, the possibility of FinFET downscaling is still open and more than ever alternatives to CMOS transistors, such as, vertically-stacked SNS-FETs are showing their potential to surpass FinFETs. Variability due to metal grain granularity (MGG) is critical at 3 nm technology nodes, as such, the device threshold voltage variation due to MGG is examined for single nanosheet NS-FET. Finally, we calculate the mean and standard deviation of these parameters to quantify the variability.

Impact of Fin Line Edge Roughness and Metal Gate Granularity on Variability of 10-nm Node SOI n-FinFET

We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi Fin n-FET due to the impact of random fluctuation sources such as gate work function variability induced by metal gate granularity (MGG) and Fin line edge roughness (LER) using quantum corrected 3-D drift diffusion (DD) simulation framework. The statistical simulation predictions reveal that for ultra downscaled SOI FinFET, the MGG predominantly affects device threshold voltage. Similarly, the LER sources are found to strongly influence the variability of device short channel effect immunity and channel mobility of carriers. Both MGG and long correlation length LER are found to strongly influence the overlap and outer fringing parasitic capacitances variability, resulting in increased variability of device intrinsic speed. It is predicted that the presence of combined random fluctuation sources results in the increased variability of threshold mismatch index ( $A_{\text {VT}}$ ) for the sub-10-nm SOI FinFET technology.

Mobility extraction for short channel UTBB-FDSOI MOSFETs under back bias using an accurate inversion charge density model

In this work we measure the inversion charge density for short UTBB-FDSOI MOSFETs (down to 45 nm) using an accurate method for the extraction of the parasitic components which take into account the effect of the back bias. Based on these results, we propose a modification of the inversion charge density model that uses the simplified Lambert function in order to include the back bias effect. This model is then validated with the experimental data for different gate lengths (from 185 nm to 45 nm). It is shown that this inversion charge model is valid for the mobility extraction and gives very good assessment of the mobility if we know only the IV-characteristic, the threshold voltage (under back bias effect) and the inversion charge capacitance. Finally, this method is used to extract the mobility for short channel devices (down to 40 nm) and it is found that the short channel mobility suffers from degradation even for large back biases. For the shortest device, it is demonstrated that the main source of mobility degradation is caused by oxide charges and interface states located near the S/D extensions and then it is deduced that the mobility reduction for large back biases is related to neutral defects from Si-crystal close to the channel edge.

Influence of gate and channel engineering on multigate MOSFETs-A review

The design of CMOS circuits using nanoscale MOSFET has become very difficult nowadays as device modeling faces new challenges such as short channel effects and mobility degradation. Gate engineering and channel engineering reduces these challenges and improves the mobility of the carriers, resulting in improved characteristics such as drain current and transconductance. In this review paper, the effect of gate and channel engineering on the characteristics (both D.C and high frequency (a.c)) of multigate MOSFETs have been investigated and presented.

Understanding short channel mobility degradation by accurate external resistance decomposition and intrinsic mobility extraction

An intrinsic short channel mobility extraction method is proposed by measuring two short-channel devices with different channel lengths and the same source/drain and contact geometry. The constant and dynamic components of external resistance are separated. Short-channel mobility degradation is observed and its origin is studied. The possible causes of the halo doping and the non-uniformity of the inversion layer charge are accounted for. The weaker temperature dependence of short channel devices indicates that the short channel mobility degradation may result from some combination of defect-induced and Coulomb-induced scattering near the S/D regions, differing in severity between NFETs and PFETs which employ, respectively, ion implant and embedded epitaxy as the primary component of S/D design.

Short channel mobility analysis of SiGe nanowire p-type field effect transistors: Origins of the strain induced performance improvement

The strain effect of three dimensionally stacked p-type SiGe nanowire field effect transistors are investigated by low temperature mobility analysis. Temperature dependent mobility behavior shows that the carrier transport of compressively strained channel is mainly limited by phonon scattering whereas impurity scattering is dominant at the unstrained short channel device. Because the compressive strain limits boron out-diffusion from the source and drain, additional impurity scattering mechanism is reduced comparing to the unstrained device. Thus, the compressively strained SiGe channel has higher immunity against short channel effect and improved effective mobility due to the limitation of dopant diffusion into the channel.

Experimental Investigation of Hole Transport in Strained $\hbox{Si}_{1 - x}\hbox{Ge}_{x}/\hbox{SOI}$ pMOSFETs: Part II—Mobility and High-Field Transport in Nanoscaled PMOS

We experimentally studied the high-field transport and mobility in nanoscaled Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 -</sub> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> Ge <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> /silicon on insulator (SOI) PMOSFETs with gate length down to 17 nm. The study relies on the electrical characterization performed from room temperature down to 20 K. Strain relaxation in short channel has been evidenced by nanobeam electron diffraction, which explains the decrease of hole velocity and mobility with gate length. Despite this strain relaxation, a mobility gain is nevertheless preserved in sub-100-nm SiGe PMOS, with a maximum gain for 20% Ge in the layer. Short-channel mobility extraction reveals a lower contribution of Coulomb scattering for SiGe channel PMOS, which may explain this mobility improvement. We also demonstrate that the short-channel transport is governed by the Ge composition in the SiGe layer, with an optimum concentration of 20% Ge. We have finally evidenced a different temperature dependence of the limiting velocity at high field between SiGe and Si PMOS, suggesting that SiGe transport will be governed by inelastic scattering instead of ballisticity as <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> is shrunk.

Method for 3D electrical parameters dissociation and extraction in multichannel MOSFET (MCFET)

A novel parameter extraction method is proposed to dissociate the current contributions of each channel in 3D Gate-All-Around multi-channel transistors. These devices, designed for CMOS low standby power architectures, exhibit well behaved characteristics and high performance. Our methodology is based on systematic measurements, numerical simulations and modeling. The substrate bias technique is used to turn ON and OFF the various channels and to remove the bottom channel contribution from the total measured current. Very high I ON/ I OFF ratios (NMOS: 2.27 mA/μm for 16 pA/μm; PMOS: 1.32 mA/μm for 16 pA/μm) are obtained experimentally as a benefit from good short-channel mobility values in each type of channel. A mobility reduction is observed in long-channel GAA transistors.

SiGe channels for higher mobility CMOS devices

AbstractSilicon germanium (SiGe) is considered to substitute silicon (Si) as channel material of p-type MOSFET in future CMOS generations due to its higher hole mobility. In this work we investigate SiGe channels with a germanium concentration of 23 at% and 30 at%, even though the mobility is expected to be higher with even more germanium in the alloy. Low pressure chemical vapor deposition was used for SiGe deposition. A state of the art CMOS process including high-k dielectric and metal gate electrode was applied for fabrication of sub 50 nm gate length devices. As expected from the SiGe channel conduction and valence band offset the threshold voltage of the devices is influenced. The gate stack was directly deposited onto the SiGe layer consisting of a chemically grown base oxide, hafnium-based dielectric and titanium nitride gate electrode. C-V and I-V measurements show comparable CET and leakage values for the high-k metal gate stack on Si and SiGe channels. The trap density at the channel dielectric interface was determined using the charge pumping technique. The device characteristics of n- and p-MOSFETs with SiGe channels are compared to conventional Si channel devices. Short channel mobility was extracted with the gM,LIN-Method.

Stress Liner Proximity Technique to Enhance Carrier Mobility in High-κ Metal Gate MOSFETs

AbstractFor the first time, we discuss the compatibility of stress proximity technique (SPT) with dual stress liner (DSL) in high-κ/metal gate (HK/MG) technology. The short-channel mobility enhancement and the drive current improvement brought by SPT have been demonstrated at 32nm technology node. With maintained short channel control and threshold voltage roll-off characteristics, SPT has achieved 7% drive current improvement for both nFET and pFET from the optimization of SPT with DSL.

Investigation of Coulomb Mobility in Nanoscale Strained PMOSFETs

This paper provides an experimental assessment of Coulomb scattering mobility for advanced strained devices. By accurate short-channel mobility extraction, we examine the impact of process-induced uniaxial strain on Coulomb mobility in short-channel pMOSFETs. Our extracted Coulomb mobility shows very weak stress dependency at room temperature. This finding has also been verified in both long- and short-channel devices by the four-point wafer bending measurement. Therefore, in order to maximize the process-induced strain efficiency on nanoscale pMOSFETs, lower surface impurity concentration is suggested to avoid the Coulomb mobility domination in carrier transport.

A Reliable Metric for Mobility Extraction of Short-Channel MOSFETs

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> When comparing the extracted carrier mobility of long- and short-channel transistors, special consideration must be given to the metallurgical gate length <formula formulatype="inline"><tex>$(L_{\rm met})$</tex></formula>, neglecting the impact of source and drain junction profiles. <formula formulatype="inline"><tex>$L_{\rm met}$</tex> </formula> can be identified with nanometer precision by using RF split-<formula formulatype="inline"><tex>$C$</tex> </formula>–<formula formulatype="inline"><tex>$V$</tex></formula> measurements, and physical and electrical analysis can demonstrate the accuracy of the method. Another important parameter, the external transistor resistance <formula formulatype="inline"><tex>$(R_{\rm sd})$</tex></formula>, can be identified with linear current measurements of short-channel devices. However, it is important to quantify the mobility dependence from the gate length in order to obtain an accurate result. A method to estimate the electrical field <formula formulatype="inline"><tex>$(E_{\rm eff})$</tex></formula> of short-channel devices is proposed. The extracted short-channel mobility shows a universal behavior identical to the classical long-channel one. </para>

Tradeoff between short channel effect and mobility in strained-Si nMOSFETs

A strained-Si CMOS technology with improved immunity to short channel effects (SCE) and reduced defect density was demonstrated at a gate length of 80 nm. The driving current was enhanced by 25% using 20% Ge content relaxed SiGe buffer. The trade-offs between electron mobility enhancement and SCE control for different Si-cap layer thicknesses and various Ge contents in the relaxed-SiGe virtual substrate are investigated. Besides, our work presents the optimum processes window for strained-Si devices in advanced CMOS technology.

Improvement of Short Channel Mobility and Operational Stability of Pentacene Bottom-Contact Transistors with a Sulfuric Acid and Hydrogen Peroxide Mixture (SPM) Treatment of Au Electrodes

ABSTRACTWe report a reduction in the contact resistance between pentacene and Au source/drain electrodes of organic field effect transistors (OFETs) with bottom-contact structure. By immersing the Au electrodes in a sulfuric acid and hydrogen peroxide mixture (SPM), the injection barrier between the Au electrodes and pentacene was lowered by approximately 0.2 eV and the contact resistance significantly decreased. The fabricated bottom-contact OFETs revealed a field-effect mobility of more than 0.66 cm2/Vs at a channel length ranging from 3 to 30 μm, which is comparable to that of top-contact OFETs with a 50 μm channel length. The transfer characteristics of the OFET with the SPM treatment were stable even after 44days storage in air under room illumination without any passivation. Moreover, the drain current reduction due to threshold voltage (Vth) shift under continuous application of gate voltage quickly recovered toward the original value with unloading of gate voltage.

Temperature Dependent Transport Parameters in Short GaN Structures

We present the mobility and diffusion constant in short GaN structures. Differential mobility decreases with increasing temperature while it increases with decreasing sample size. Theoretically calculated transconductance of an AlGaN/GaN HEMT, using the short channel mobility, is in good agreement with experimental data.

Four Level Simulation of MOSFET

In this paper a software (MOSOFT) has been developed for 4-level simulation of MOSFETS. This software simulates the device characteristics up to micron channel length and includes long channel, short channel, subthreshold and field dependent mobility degradation models.