Tradeoff between short channel effect and mobility in strained-Si nMOSFETs

Abstract

A strained-Si CMOS technology with improved immunity to short channel effects (SCE) and reduced defect density was demonstrated at a gate length of 80 nm. The driving current was enhanced by 25% using 20% Ge content relaxed SiGe buffer. The trade-offs between electron mobility enhancement and SCE control for different Si-cap layer thicknesses and various Ge contents in the relaxed-SiGe virtual substrate are investigated. Besides, our work presents the optimum processes window for strained-Si devices in advanced CMOS technology.