Shifter Architecture Research Articles

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

The objective of this study is to present a level shifter architecture that utilizes a pair of inverters and a Wilson current mirror to reduce power consumption while improving voltage shifting capabilities. We introduce novel components such as super-cut-off pull-down and stacked pull-up networks to effectively minimize leakage power. Our design leverages multi-threshold CMOS (MTCMOS) technology, incorporating sleep transistors to boost operational speed, decrease power consumption, and reduce the physical footprint. The proposed circuit is engineered to step up voltage levels, ranging from a mere 0.4 V to a substantial 1.2 V. Through extensive optimization of performance parameters, including power efficiency, delay, and area utilization, we have tailored this design to cater specifically to the demands of nano-scale applications. Key results from our research reveal that the average active power consumption for “level-up” shifts is impressively low at 48.5 nW, with an average latency of a mere 1.58 ns for 1 MHz transmission frequencies. Post-layout modeling demonstrates that our suggested design occupies a compact area of just 9.97 µm2. These findings were meticulously modeled using Cadence Virtuoso with 45 nm processes. Furthermore, our research highlights the substantial advancements achieved when compared to previous methods. The proposed design boasts a threefold increase in operational speed and delivers significant savings in both area and power consumption. These outcomes have far-reaching implications for emerging technologies and applications in the field.

Analysis and Design of a Ku-Band Bidirectional Time-Varying Vector-Sum Phase Shifter in 0.13-μm CMOS Technology

This brief describes a Ku-band passive time-varying phase shifter (TVPS). The time variable is introduced into the conventional vector-sum phase shifter (VSPS) architecture, and the time-varying vector-sum method is proposed for the first time to realize continuous phase shifting. The proof-of-concept passive TVPS consisting of a quadrature coupler, two 0/180° bi-phase modulators and an output combiner is implemented in 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {\mathrm {\mu }}\text{m}$ </tex-math></inline-formula> CMOS technology with a core area of 2.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {\times }$ </tex-math></inline-formula> 0.8 mm2, and a field-programmable gate array (FPGA) is used to provide gain-control timing sequences with the modulation frequency of 100 kHz for its four control bits. The timing sequences are optimized to eliminate unwanted sidebands, and the measured sideband suppression ratio (SSR) is −17.2 dBc. For both forward and backward phase shifting modes, measured results show that the proposed TVPS can achieve the phase resolution of 10-bits, RMS phase error of 0.2~0.5°, RMS gain error of less than 0.2 dB over the 12~18 GHz frequency band.

CMOS variable-gain phase shifter based on time-varying vector-sum method and its application to Ku-band phased array

In this paper, a new time-varying vector-sum method is proposed for variable-gain phase shifter design. By introducing a time variable into the conventional vector-sum phase shifter (VSPS) architecture, high-resolution phase shifting and wide amplitude control can be achieved simultaneously. The proposed time-varying phase shifter (TVPS) is fabricated in 0.13-μm CMOS technology with a core area of 1.76 mm2. A field-programmable gate array (FPGA) is utilized to generate gain-control timing sequences for phase shifting and on-off timing sequence for amplitude control, which are optimized to achieve a measured sideband suppression ratio of −17.2 dBc. For bidirectional operation, measured results present that the proposed TVPS can achieve a phase resolution of 10-bits, RMS (root mean square) phase error of 0.2–0.5°, RMS gain error of less than 0.2 dB, and gain tuning range of 10.1 dB in the frequency band of 12–18 GHz. The proposed TVPS is applied to a 4-element phased array, and the measured radiation patterns of scanned beams are presented.

Contention Mitigation based Level Shifter Architecture

Energy efficiency is one of the most important issues that needs to be solved in the current system on chip design. To overcome this issue, many circuits inside the chip run at low power. However there are some blocks like memories that run at relatively higher voltages. This means, modern day SOC contains different voltages running through it. The problem arises when two blocks operating at different voltages want to communicate with each other. This problem is solved by using Level Shifters as an interfacer between the blocks. The function of Level Shifter is to convert voltage level of input signal to that of the output. In this paper a cross coupled architecture of Level Shifter is proposed which operates between 1.5v and 5v. The speciality of this architecture is there is less contention between pull up network and pull down network, which reduces the rise and fall delay significantly. The proposed design is simulated at different operating conditions and the functionality is checked.

Realization of 8 x 4 Barrel shifter with 4-bit binary to Gray converter using FinFET for Low Power Digital Applications

Barrel shifter architecture is well known for bit manipulation in a single clock cycle. Due to its various operations and advantages, it is most likely used in the Arithmetic logic unit of every processor. Gray code is also known as reflective code which is widely used in digital communication for the purpose of error correction and error detection. In this project, an 8 x 4 barrel shifter is designed which is further connected to 4-bit binary to gray code converter. The barrel shifter is cascaded with binary to gray code converter so that this combination can be useful for the application of encryption of binary data in digital communications. It is designed in cadence virtuoso tool using FinFET technology at 18 nm node. The simulation results proves that the power consumed by the proposed design with FinFET technology is 11.92% less when compared with the conventional design with MOS transistors. Hence, this design can be used in application of low power digital communications. The functionality testing and verification is done using cadence virtuoso tool.

A modulator-less beam steering transmitter based on a revised DDS-PLL phase shifter architecture

This paper details the design and implementation of a modulator-less beam steering transmitter based on a revised DDS-PLL phase shifter architecture. The proposed topology targets low data rate communications for Internet-of-Things systems, and has been demonstrated using an FPGA evaluation board and a custom PCB with four PLLs centered at 2.453-GHz. Measured system performance for an experimental 32-kbps data rate achieved through a 16-PSK modulation scheme are discussed. The proposed architecture is frequency independent, can be used in multi-band devices and has the potential for being integrated as an RF System-on-Chip.

Coherent solid-state LIDAR with silicon photonic optical phased arrays.

We present, to the best of our knowledge, the first demonstration of coherent solid-state light detection and ranging (LIDAR) using optical phased arrays in a silicon photonics platform. An integrated transmitting and receiving frequency-modulated continuous-wave circuit was initially developed and tested to confirm on-chip ranging. Simultaneous distance and velocity measurements were performed using triangular frequency modulation. Transmitting and receiving optical phased arrays were added to the system for on-chip beam collimation, and solid-state beam steering and ranging measurements using this system are shown. A cascaded optical phase shifter architecture with multiple groups was used to simplify system control and allow for a compact packaged device. This system was fabricated within a 300mm wafer CMOS-compatible platform and paves the way for disruptive low-cost and compact LIDAR on-chip technology.

Low energy/delay overhead level shifter for wide‐range voltage conversion

SummaryMulti‐supply voltage systems on chip have been widely explored for energy‐efficient elaborations. A main challenge of multi‐supply voltage designs is the interfacing of digital signals coming from ultra‐low‐voltage core logics to higher power supply domains and/or to input/output circuits. In this work, we propose an energy/delay‐efficient level shifter architecture that is capable of converting extremely low levels of input voltages to the nominal voltage domain. In order to limit static power, the proposed circuit is based on the single‐stage differential cascode voltage switch scheme. To improve switching speed and dynamic energy consumption, our design dynamically adapts the current sourced by the pull‐up network on the basis of the occurring transition. A test chip was fabricated in 180 nm complementary metal–oxide–semiconductor technology to verify the proposed technique. Measurement results show that our design is capable of converting 100 mV of input voltages to 1.8 V, while assuring an average propagation delay of about 26 ns, an average static power of 100 pW, and an energy per transition of 140 fJ for the target voltage‐level conversion from 0.4 to 1.8 V. Copyright © 2016 John Wiley &amp; Sons, Ltd.

A new CMOS all-pass phase shifter for phased array systems

A new tunable all-pass phase shifter architecture based on current mirror, with low complexity and power consumption is proposed in 0.18um CMOS, after a brief introduction on phase shifter applications. In the new current-mode approach the cut-off frequency of transistor is the operational limit of the proposed phase-shifter architecture and power consumption for this design is 80 microwatts. Simulations are carried out in HSpice and cover a frequency range from 1MHz to about 50GHz.

A Timing-Driven Approach to Synthesize Fast Barrel Shifters

In modern digital signal processing and graphics applications, the shifter is an important module, consuming a significant amount of delay. This brief presents an architectural optimization approach to synthesize a faster barrel shifter block, which can be useful to reduce the delay of the design without significantly increasing the area. We have divided the problem of generating the shifter into two steps: (i) timing-driven selection of multiple stages for merging, and (ii) the design of the merged stage. In our proposed method, we define the notion of dual merged stage, where two stages are merged and the triple merged stage, where three stages are merged into a single composite stage. These merged stages are identified by using a timing-driven algorithm and are used in conjunction with some single stages of the traditional barrel shifter. The use of these merged stages helps reduce the depth of the proposed barrel shifter architecture, thereby improving the delay. The timing-driven nature of our algorithm helps produce a faster implementation for the overall shifter block. We have evaluated the performance of our design by using a number of technology libraries, timing constraints and shifter bit-widths. Our experimental data shows that the shifter block generated by our algorithm is significantly faster (10.19% on average) than the shifter block generated by a commercially available datapath synthesis tool. These improvements were verified on placed-and-routed designs as well.

Single-chip integrated electro-optic polymer photonic RF phase shifter array

This paper demonstrates a four-element integrated photonic radio-frequency (RF) phase shifter array in a single chip with an advanced configuration. These devices are integrated using electrooptic polymer materials and involve several novel technologies. Measurements of this configuration showed that our four outputs were independent and had highly linear RF phases over 360° with negligible RF power fluctuation at the modulation frequency of 20 GHz. This significant improvement is capable of removing one of the major problems in using this type of phase shifter architecture.

A Universal Shifter with Packed Data Formats

In this letter, we propose a universal shifter architecture which executes parallel vector shift operations as well as data reorganizing operations concerning packed data formats. The universal shifter is beneficial in cost-effectively implementing microprocessors' SIMD ISA extensions. It reduces the overall occupied area by 56% and delay time by 6% compared to the conventional implementations which have duplicated operational units.

A new digital phase shifter architecture suitable for MMIC's

A new architecture is proposed for digital phase shifters that is suitable for monolithic integration (MMIC's). It consists of an arrangement of a standard building block which is a vector summer and limiter repeated many times over the circuit. Examples of phase shifters up to 6 b are given. Other arrangements of these blocks are mentioned, which give rise to new possibilities.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>