Shift Register Circuit Research Articles

General Structure and Properties of Cyclic Codes Over \(GF_2\)

This article provides a comprehensive analysis of cyclic codes in GF(2), focusing on their general structure and key properties. Cyclic codes are characterized by their generator polynomials, which define their structure and play a crucial role in encoding and decoding processes. The cyclical shift property, inherent in cyclic codes, facilitates efficient implementation using shift register circuits, making them practical for real-world applications. The discussion highlights the algebraic properties that distinguish cyclic codes from other linear block codes, emphasizing their ability to detect and correct errors.

Efficient Design and Implementation of QCA SISO Shift Register Circuits for Nanocomputing

The most promising emerging technology that can reduce the power, area and delay in digital circuits is Quantum-dot Cellular Automata (QCA) technology. The Serial Input-Serial Output (SISO) Shift Register (SR) is a basic component in digital circuits. The SISO SR can be designed using two methods in the QCA technology, directly mapping circuits from the CMOS technology and using the inherent capability of the QCA technology. This paper presents and evaluates the new [Formula: see text]-bit QCA SISO SR that not only uses the inherent capability of QCA technology but also has a regular architecture. The proposed [Formula: see text]-bit SISO SR is developed based on the building block, which is designed in this paper. In addition, the developed QCA SISO SR has coplanar architecture and it has the ability to correct or change data. The proposed [Formula: see text]-bit SISO SR is evaluated for 3, 4 and 5 bits using QCADesigner-[Formula: see text]. The results demonstrate that the designed circuits for 3-, 4- and 5-bit QCA SISO SRs require 68 (0.06 [Formula: see text]m[Formula: see text], 92 (0.08[Formula: see text][Formula: see text]m[Formula: see text] and 116 (0.09[Formula: see text][Formula: see text]m[Formula: see text] cells (area), respectively. The comparison demonstrates that the developed QCA SISO SRs have advantages in comparison to other QCA SISO SR circuits.

39‐1: Invited Paper: An Improved Gate Driver Using Oxide TFTs for Large OLED Displays

In this paper, we present the small area and high reliable gate driver in panels using a‐IGZO TFTs for large OLED displays. The proposed gate driver circuit has a small area structure with multiple output buffers connected to one shift register circuit. To lower the voltage stress of the pull‐down TFTs, which have the highest voltage stress among the TFTs of the gate driver, the initial voltage of those TFTs is set to low and increases according to the threshold voltage shift of TFTs during operation. It could be implemented by sensing the degradation of the TFTs using the programmable DC driving method. With these technologies, we were able to reduce the gate driver design area by 40% and improve the reliability by 30% despite reducing the circuit area. We successfully developed OLED TVs from 42 inches to 97 inches using the proposed gate driver.

High-performance LFSR circuit design based on XOR gates

The research discussed in this article is focused on analysing the effects of XOR gates based on different logic families, namely MOS Current Mode Logic (MCML), dynamic current logic, and PTL, on the performance of linear feedback shift register (LFSR) circuits. The aim of the study is to evaluate the power dissipation and critical path latency of the circuits while comparing the results with earlier works in the field. To achieve this, the researchers implemented the 3, 4, and 5-bit LFSR circuits using Verilog HDL code and synthesized them on the Cadence tool using 90nm CMOS technology. The study concludes that LFSR circuits based on XOR gates outperform previous LFSR circuits in terms of power dissipation. The research also offers a comparative analysis of the different types of XOR gates used in the LFSR circuits, highlighting the advantages and disadvantages of each type. The results of the study can be useful for researchers working in the field of circuit design, as well as for practitioners who are interested in developing low-power and efficient LFSR circuits.

High Performance Amorphous In0.5Ga0.5O Thin‐Film Transistor Embedded with Nanocrystalline In2O3 Dots for Flexible Display Application

AbstractHigh‐performance, coplanar amorphous In0.5Ga0.5O (a‐IGO) thin film transistor (TFT) on a polyimide (PI) substrate deposited by spray pyrolysis (SP) is reported. The SP a‐IGO film deposited at 370 °C has less than 8% nanocrystalline‐In2O3 dots and a mass density of 6.6 g cm−3. The a‐IGO TFT on PI exhibits linear mobility over 30 cm2 V−1 s−1 and a negligible shift in threshold voltage (ΔVTH = <0.3 V) under positive bias (+20 V) at 60 °C for 1 h. The TFT performance is stable even when bent to a radius of ≈1 mm. The X‐ray photoelectron spectroscopy results of the SP a‐IGO deposited at 370 °C indicate the O‐vacancy (Vo) related defects of 25.79% and hydroxyl (OH) at less than 3%, indicating a good active/gate insulator interface. A seven‐stage ring oscillator made of SP a‐IGO TFTs exhibits a high oscillation frequency (>2.3 MHz) with a low propagation delay time of ≈30 ns per stage at a supply voltage (VDD) of 15 V. The fabricated gate shift register circuit works up to the last stage without any decrement of the input voltage (15 V) with rising and falling times less than 0.8 µs. Therefore, the coplanar a‐IGO TFT by SP deposited at 370 °C is a promising candidate for low‐cost, flexible TFT backplanes of foldable electronics.

High-Speed Shift Register with Dual-Gated Thin-Film Transistors for a 31-Inch 4K AMOLED Display.

In this work, a promising dual-gated thin film transistor (TFT) structure has been proposed and introduced in the shift register (SR)-integrated circuits to reduce the rising time. The threshold voltage can be simultaneously changed by the top gate and the bottom gate in the proposed dual-gated TFTs. When the SR circuits start to export the scan signals in the displays, the driving currents in the SR circuits are increased by switching the working station of driving TFTs from the enhancement characterization to the depletion characterization. Subsequently, the detailed smart spice simulation has been used to study the function of the proposed SR circuits. In the next step, the proposed SR circuits have been fabricated in a G4.5 active-matrix organic light-emitting diode manufacture factory. The simulated and experimental results indicate that the shift register pulses with the full swing amplitude can be obtained in the SR circuits. Moreover, in contrast to the conventional SR circuits employing with the single-gated TFTs, it has been found that the rising time of the output signals can be reduced from 3.75 μs to 1.23 μs in the proposed SR circuits with the dual-gated TFTs, thus exhibiting the significant improvement of the driving force in the proposed SR circuits. Finally, we demonstrated a 31-inch 4K AMOLED display with the proposed SR circuits.

P‐38: Low‐Power a‐IGZO TFT Shift Register Featuring i‐PUA Gate Dielectric

In this paper, a low‐power shift register circuit based on coplanar a‐IGZO TFTs using photo‐patternable micron‐sized i‐PUA is proposed for next‐generation display. We confirmed that the fabricated shift register circuit consisting of six coplanar a‐IGZO TFTs and one capacitor successfully operates with low‐power driving within 3 V at various frequencies.

P‐43: Finely Programmable Pulse Width Shift Register for Luminance Control of AMOLED Displays

In this paper, we propose a programmable shift register circuit at a low temperature poly‐silicon (LTPS) backplane suitable for high‐resolution and high‐speed displays. The proposed circuit can control the pulse width at a line‐time unit by a start signal, where two additional clock signals were in use compared to the conventional circuit. Smartspice simulation was conducted to verify the feasibility, proving the pulse width controllability at a line‐time unit. The estimated power consumption is lower than the conventional circuit.

Novel Circuits Design for SISO Shift Register in QCA Technology

The quantum-dot cellular automata technology has great attention in nanoscale digital circuits design due to its high-speed and high-dense. Shift registers play vital role in digital circuits design. So, efficient implementation of shift register circuits in this technology is in the focal point of researches in digital circuits design. In this study, new structures are proposed for the shift register circuits in single layer, three layers and five layers based on inherent quantum-dot cellular automata clock. The QCADesigner tool version 2.0.3 is employed for simulation and verification of functionality of the proposed structures for the serial-input-serial-output shift register circuits. The results demonstrate that the developed 3-bit, 4-bit and 5-bit coplanar shift register circuits require 32, 44 and 56 cells, respectively. The comparison results demonstrate that the developed circuits provide advantages compared to other circuits in terms of area, cell count, clock cycles and cost.

Efficient Designs of Reversible Shift Register Circuits with Low Quantum Cost

Reversible computations have attracted a lot of attention in recent years due to the ability to reduce energy dissipation that is needed in nanocircuits. The main purpose of designing reversible circuits is to reduce the energy consumption that occurs due to the loss of input bits in irreversible circuits. In this paper, we initially proposed a new [Formula: see text] reversible block and then its quantum realization is given using the Miller et al. method. In the following, an effective reversible design of D flip-flop is introduced using the proposed reversible block. Finally, four types of reversible shift register including serial-in to parallel-out (SIPO), parallel-in to parallel-out (PIPO), parallel-in to serial-out (PISO) and shift counter are proposed using the proposed reversible flip-flop. The evaluation results show that the proposed circuits are superior compared to the existing designs in terms of quantum cost (QC).

Optimal concurrency on FPGA for lightweight medical image encryption

Digitized forms of images do widely used for medical diagnostics. To maintain the privacy of an individual in e-health care applications, securing the medical image becomes essential. Hence exclusive encryption algorithms have been developed to protect the confidentiality of medical images. As an alternative to software implementations, the realization of image encryption architectures on hardware platforms such as FPGA offers significant benefit with its reconfigurable feature. This paper presents a lightweight image encryption scheme for medical image security feasible to realize as concurrent architectural blocks on reconfigurable hardware like FPGA to achieve higher throughput. In the proposed encryption scheme, Lorentz attractor’s chaotic keys perform the diffusion process. Simultaneously, the pseudo-random memory addresses obtained from a Linear Feedback Shift Register (LFSR) circuit accomplishes the confusion process. The proposed algorithm implemented on Intel Cyclone IV FPGA (EP4CE115F29C7) analyzed the optimal number of concurrent blocks to achieve a tradeoff among throughput and resource utilization. Security analyses such as information entropy, histogram, correlation, and PSNR confirms the algorithm’s encryption quality. The strength of diffusion keys was ensured by randomness verification through the standard test suite from the National Institute of Standards and Technology (NIST). The proposed scheme has a larger keyspace of 2384 that guarantees good confusion through near-zero correlation, and successful diffusion with a PSNR of <5 dB towards the statistical attacks. Based on the hardware analysis, the optimal number of concurrent architectural blocks (2 N) on the chosen FPGA to achieve higher throughput (639.37 Mbps), low power dissipation (138.85 mW), minimal resource utilization (1268 Logic Elements) and better encryption quality for the proposed algorithm is recommended as 4 (with N = 2).

Research on the Bias Network of Energy-Efficient Single Flux Quantum Circuits

Superconducting single flux quantum (SFQ) circuits have been shown to offer huge advantages that are ideal for high performance computing applications. These circuits can operate at very high frequencies (tens of GHz) but consume very low power (from nanowatts to microwatts per gate). Energy-efficient SFQ (ERSFQ) circuits, evolved from traditional rapid SFQ (RSFQ) circuits, were invented with the goal of elimination of static power dissipation. When compared with RSFQ circuits, ERSFQ circuits require a new biasing network that includes biasing Josephson junction(s), biasing inductor(s), and feeding Josephson transmission line(s). Some general suggestions on how to design the network have been offered, but a detailed analysis and optimization scenario for the network is still to be provided. In this paper, we first optimize the previously reported DC-biased two-Josephson junction per bit RSFQ shift register circuit, which can be used to provide a more robust, energy-efficient, and high memory capacity storage unit. The simulated power dissipation of 16-bit RSFQ shift register is 0.45 μW per bit when operating at 21.7 GHz. We then convert the RSFQ-based shift register into an ERSFQ structure and investigate the effects of the ERSFQ bias network on the margins of the ERSFQ circuit. Finally, we propose a more comprehensive optimization method for the ERSFQ biasing network.

Improving Error Correction Stage and Expanding the Final Key using Dynamic Linear-feedback Shift Register in Sarg04 Protocol

The mechanism of quantum mechanics is considered as the principal method of quantum key distribution for transmitting a cryptographic key between users in unconditionally secure communication. In this paper, simulation and enhancement of the performance of SARG04 protocol have been done in terms of error correction stage using multiparity rather than single parity. In addition, the suitable length of subblock was selected depending on the values of quantum bit error rate and round number. Dynamic linear-feedback shift register circuits have been used to extend the final key. These circuits are dynamically generated by the final key. A unique linear circuit is created for each generated key.

A Construction of High Performance Quasicyclic LDPC Codes: A Combinatoric Design Approach

This correspondence presents a construction of quasicyclic (QC) low-density parity-check (LDPC) codes based on a special type of combinatorial designs known as block disjoint difference families (BDDFs). The proposed construction of QC-LDPC codes gives parity-check matrices with column weight three and Tanner graphs having a girth lower-bounded by 6. The proposed QC-LDPC codes provide an excellent performance with iterative decoding over an additive white Gaussian-noise (AWGN) channel. Performance analysis shows that the proposed short and moderate length QC-LDPC codes perform as well as their competitors in the lower signal-to-noise ratio (SNR) region but outperform in the higher SNR region. Also, the codes constructed are quasicyclic in nature, so the encoding can be done with simple shift-register circuits with linear complexity.

Контролепригодность схем в FPGA-проектах по признаку рассеиваемой мощности

The authors consider the checkability issues of FPGA designs and analyze the logical (structural and structurally functional) checkability. The paper describes the features of safety-related systems that can operate in normal and emergency mode. In these modes different input data are fed to the inputs of the digital circuits of the components, which leads to an expansion of the structurally functional checkability to dual-mode. The paper shows the problem of hidden faults, which can accumulate in the normal mode and manifest themselves in the emergency mode. The features of checkability of circuits in FPGA projects and its advantages important for critical applications are noted. The limitations of the logical checkability of the circuits are analyzed, as well as the possibility and expediency of expanding the traditionally used logical form to power usage checkability. The study defines the checkability of circuits in FPGA projects by power usage and determines its subtypes — lower and upper checkability. Lower checkability is important in identifying faults that lead to lower power usage, for example, in chains of common signals, such as reset or synchronization. The upper one is important for identifying faults that increase the level of power usage, for example, short-circuits. The authors identify the possibility of assessing the power usage checkability of FPGA projects in terms of the power dissipation or power consumption and indicate the possibility of developing upper checkability by the dissipated power. The features of power dissipation monitoring for FPGA projects are noted. An analytical assessment for the checkability of circuits for short-circuit faults, which increase the dissipated power, and the organization of monitoring its excess are proposed. Experiments in Quartus Prime Lite CAD to assess upper checkability by power dissipation of scalable shift register circuits, that are implemented in FPGA projects, based on default IP-Core and a custom VHDL description, are carried out. The paper presents experimental results, that estimate the dependence of the checkability level on the area, occupied by the circuit on the FPGA chip.

Low Power and Low Noise Shift Register for In-Cell Touch Display Applications

This paper proposes a shift register circuit integrated in in-cell touch display panels that achieves low power operation, low coupling noise, and high long-term reliability with 11 thin film transistors (TFTs) and two capacitors. A time division driving method is utilized to prevent the crosstalk of display signals into touch circuits, and two pre-charging nodes are employed to relieve the uniformity degradation of output signals caused by different stresses on pull-up TFTs. The proposed circuit activates a drain of the first pre-charging TFT only at display scanning periods, which reduces coupling noises and power consumption. In addition, an internal inverter is turned off for touch sensing operations, resulting in a wide range of threshold voltage shift compensation and low power consumption. SPICE simulation results with a low temperature poly silicon TFT model show that the proposed circuit compensates for the threshold voltage shift up to 17 V. In a 60 Hz full-HD display with a 120 Hz touch reporting rate, the noise level of the first pre-charging node is −16.78 dB in between 2.37 and −28.95 dB of two previous circuits, and the total power consumption for 160 stages is substantially reduced to 4.44 mW compared to previous approaches.

Robust integrated shift register circuit over clock noises for in‐cell touch applications

AbstractThis paper proposes an integrated shift register circuit for an in‐cell touch panel that is robust over clock noises. It is composed of 10 thin film transistors and 1 capacitor, and the time division driving method is adopted to prevent the negative effect of display signals on the touch sensing. Two pre‐charging nodes are employed for reducing the uniformity degradation of gate pulses over time. In particular, the proposed circuit connects a drain of the first pre‐charging node's pull‐up thin film transistor (TFT) to the positive supply voltage instead of clock signals. This facilitates to lower coupling noises as well as to clock power consumption. The simulation program with an integrated circuit emphasis is conducted for the proposed circuit with low temperature poly‐silicon TFTs. The positive threshold voltage that shifts up to 12 V at the first pre‐charging pull‐up TFT can be compensated for without the uniformity degradation of gate pulses. For a 60‐Hz full‐HD display with a 120‐Hz reporting rate of touches, the clock power consumption of the proposed gate driver circuit is estimated as 7.13 mW with 160 stages of shift registers. In addition, the noise level at the first pre‐charging node is lowered to −28.95 dB compared with 2.37 dB of the previous circuit.

9‐1: An Ultra‐narrow Border of In‐cell Touch TFT‐LCD by Using TGP and OTSD Technology with New S/R Circuit

We manufacture an ultra‐narrow border of TFT‐LCD with in‐cell touch function. For the narrow border panel, we using One Third Source line Driving(OTSD) and Tracking Gate line in Pixel(TGP) technology. We set new shift register (S/R) circuit at the top side border of display. And we combine the new S/R and TGP technology to make an ultra‐narrow border mobile phone panel. By OTSD technology, we set the gate lines in the area that is source lines originally, and keep the aperature ratio at the same time. A 5 inch FHD untra‐narrow border(0.35mm) with in‐cell touch fuction display was demonstrated.

42‐3L: Late‐News Paper: Development of Crystalline IGZO and LTPS Hybrid TFTs Array Technology

Because of the unique property, the low leakage current of crystalline indium gallium zinc oxide (c‐IGZO) thin film transistors (TFTs), it can archive the low power consumption of a panel within low frame rate driving. Low temperature poly‐silicon (LTPS) TFTs as components of shift register circuit can fulfill small border size. The c‐IGZO TFTs for pixel switch and the LTPS TFTs for gate driver on array backplane have been both deposited on glass substrate. We demonstrate a prototype of 1.4 inch circular LCD with c‐IGZO and LTPS hybrid backplane technology to achieve small border size and low power consumption. And the panel shows good picture quality without flickering when very low frame rate driving (6Hz). In addition, the optical property and crystallinity of c‐IGZO have been studied in this work.

Operational efficiency of novel SISO shift register under thermal randomness in quantum-dot cellular automata design

For nano scale logic circuit, device area and power consumption are the major concerns. In this paper, the design of an optimized SISO shift register is explored based on quantum-dot cellular automata (QCA) device. The design is achieved in a single layer. To design the shift register circuit, a new QCA D flip-flop has been proposed. These new D flip-flop has minimum cell count and lower device area over existing designs. The proposed shift register also outperforms the existing designs by reducing cell count and area. The power consumption by the proposed design is carried out that shows the low energy consumption nature of the circuit. Logic gate, QCA cell and device density have been considered to evaluate the circuit. Simulation timing diagram and truth table of the proposed circuits are compared which shows that all the designs are functioning efficiently. Stability under thermal randomness for all the designs are analyzed which shows the steadiness of the designs. The impacts of control input, i.e., clock on the designs are explored. Besides the defects in proposed QCA layouts are also identified and excelled for fault free implementation.