Контролепригодность схем в FPGA-проектах по признаку рассеиваемой мощности

Abstract

The authors consider the checkability issues of FPGA designs and analyze the logical (structural and structurally functional) checkability. The paper describes the features of safety-related systems that can operate in normal and emergency mode. In these modes different input data are fed to the inputs of the digital circuits of the components, which leads to an expansion of the structurally functional checkability to dual-mode. The paper shows the problem of hidden faults, which can accumulate in the normal mode and manifest themselves in the emergency mode. The features of checkability of circuits in FPGA projects and its advantages important for critical applications are noted. The limitations of the logical checkability of the circuits are analyzed, as well as the possibility and expediency of expanding the traditionally used logical form to power usage checkability. The study defines the checkability of circuits in FPGA projects by power usage and determines its subtypes — lower and upper checkability. Lower checkability is important in identifying faults that lead to lower power usage, for example, in chains of common signals, such as reset or synchronization. The upper one is important for identifying faults that increase the level of power usage, for example, short-circuits. The authors identify the possibility of assessing the power usage checkability of FPGA projects in terms of the power dissipation or power consumption and indicate the possibility of developing upper checkability by the dissipated power. The features of power dissipation monitoring for FPGA projects are noted. An analytical assessment for the checkability of circuits for short-circuit faults, which increase the dissipated power, and the organization of monitoring its excess are proposed. Experiments in Quartus Prime Lite CAD to assess upper checkability by power dissipation of scalable shift register circuits, that are implemented in FPGA projects, based on default IP-Core and a custom VHDL description, are carried out. The paper presents experimental results, that estimate the dependence of the checkability level on the area, occupied by the circuit on the FPGA chip.