Shift Register Circuit Research Articles

7.3: Depletion‐Mode Oxide‐TFT Shift Register with Wide Operating Frequency Range for AMOLED Displays

This paper proposed a shift register circuit for GIP (Gate driver In Panel) in active matrix organic light emitting diode displays which enable cost innovation and narrow bezel. The shift register circuit which is made up with depletion mode oxide TFTs is designed to be driven at low operation frequency for power reduction in still image as well as to be driven at high operation frequency for motion picture quality improvement in moving image. However, it is especially difficult to operate at low frequency because oxide TFTs easily have negative Vth and zero gate‐source voltage turns out to be unable to shut down current path. The proposed shift register is integrated in a 15‐inch HD (1366 × 768, 105ppi) AMOLED panel, it is ensured that the shift register have wide operating frequency range from 1Hz to 240 Hz. In Addition, it is verified that the panel operates at high temperature(60°C) during 1,000 hours without any problems.

(Invited) Integrated Gate Driver Circuits Using a-Si TFT and Oxide TFT

The gate driver circuits using the a-Si TFT and oxide TFT are reviewed. Based on the analysis of the failure behavior of a shift register circuit, various schematics designed for enhanced stability are given with the introduction of clamping voltage as a measure of the degradation of a circuit. For embedding oxide TFT circuits, the scheme for applying offset bias is suggested and its effect on stability is described. Finally, practical issues such as the circuits for smaller area and the optimum design in a confined area for better performance is discussed.

Depletion Mode Oxide TFT Shift Register for Variable Frame Rate AMOLED Displays

This letter demonstrates a shift register circuit at the backplane of depletion mode oxide thin-film transistors (TFTs), which can cover variable frame rates for low-power active matrix organic light emitting diode (AMOLED) displays. The proposed scheme focuses on the stable gate control of a pull-up TFT by securing the charging and discharging paths at the wide operating frequency range. In a prototype high-definition (HD: 1366 × 768) AMOLED panel, it is ensured that fabricated shift registers operate at the wide frame frequency range from 1 to 240 Hz. The measured current consumptions are 30, 4, 6, and 5.8 mA for four clock signals, VGH of 24 V, VGL1 of -6 V, and VGL2 of -14 V at a frame rate of 120 Hz.

Dualities and identities for entanglement-assisted quantum codes

The dual of an entanglement-assisted quantum error-correcting (EAQEC) code is the code resulting from exchanging the original code’s information qubits with its ebits. To introduce this notion, we show how entanglement-assisted repetition codes and accumulator codes are dual to each other, much like their classical counterparts, and we give an explicit, general quantum shift-register circuit that encodes both classes of codes. We later show that our constructions are optimal, and this result completes our understanding of these dual classes of codes. We also establish the Gilbert–Varshamov bound and the Plotkin bound for EAQEC codes, and we use these to examine the existence of some EAQEC codes. Finally, we provide upper bounds on the block error probability when transmitting maximal-entanglement EAQEC codes over the depolarizing channel, and we derive variations of the hashing bound for EAQEC codes, which is a lower bound on the maximum rate at which reliable communication over Pauli channels is possible with the use of pre-shared entanglement.

Conception and Implementation of a BCH Code on a FPGA Board

In this paper we have designed and implemented a BCH (15, 7, 5) encoder on FPGA using VHDL description language and we implanted it on an FPGA Spartan 3E Starter board. The digital logic implementation of binary encoding of multiple error correcting BCH code of length n=15 is organized into shift register circuits. Multiple characteristics of cyclic codes will be discussed further on. The results of the simulation and implementation using Xilinx ISE.12.1 software and the LCD screen on the FPGAs Board will be shown at last.

Comparison of Static and Dynamic Printed Organic Shift Registers

Dynamic and static shift-register circuits are fabricated with an inkjet process for printing complementary organic semiconductors. The static design is based on edge-triggered master-slave flip-flops, and the dynamic design is based on a true-single-phase-clock architecture. The merits and drawbacks of the two approaches are considered and compared.

Design and Implementation of Encoder for (15, k) Binary BCH Code Using VHDL and eliminating the fan-out

In this paper we have designed and implemented(15, k) a BCH Encoder on FPGA using VHDL for reliable data transfers in AWGN channel with multiple error correction control. The digital logic implementation of binary encoding of multiple error correcting BCH code (15, k) of length n=15 over GF (2 4 ) with irreducible primitive polynomial x 4 +x+1 is organized into shift register circuits. Using the cyclic codes, the reminder b(x) can be obtained in a linear (15-k) stage shift register with feedback connections corresponding to the coefficients of the generated polynomial. Three encoder are designed using VHDL to encode the single, double and triple error correcting BCH code (15, k) corresponding to the coefficient of generated polynomial. Information bit is transmitted in unchanged form up to k clock cycles and during this period parity bits are calculated in the LFSR then the parity bits are transmitted from k+1 to 15 clock cycles. Total 15-k numbers of parity bits with k information bits are transmitted in 15 code word. Here we have implemented (15, 5, 3), (15, 7, 2) and (15, 11, 1) BCH code encoder on Xilinx Spartan 3 FPGA using VHDL and the simulation & synthesis are done using Xilinx ISE 13.3. BCH encoders are conventionally implemented by linear feedback shift register architecture. Encoders of long BCH codes may suffer from the effect of large fan out, which may reduce the achievable clock speed. The data rate requirement of optical applications require parallel implementations of the BCH encoders. Also a comparative performance based on synthesis & simulation on FPGA is presented. Keywords: BCH, BCH Encoder, FPGA, VHDL, Error Correction, AWGN, LFSR cyclic redundancy checking, fan out .

Selected Mapping Technique for PAPR Reduction Without Side Information Based on m-Sequence

Selected mapping (SLM) is a technique for reducing the high peak-to-average power ratio (PAPR) in which a suitable signal is selected among a set of alternative signals which all indicate alike information. The chief drawback existing in this method is that transmitter is compelled to send several additional bits called side information (SI) for each data block in order that recovering at the receiver side can be possible. In this paper, we present a novel SLM scheme by using the linear feedback shift register circuit and m-sequence named MSLM technique by which any side information bit is not explicitly sent. In MSLM, The basic idea is to fit the side information into transmitted symbols based upon which some special locations in the transmitted data block are expanded, i.e. some transmitted symbols are extended. In the receiver side, by using some properties of m-sequence the SI bits can be detected. We present the example of our method for an OFDM system through the use of 16-QAM modulation and different m-sequences and finally, concerned results are illustrated from the view point of bit error rate, probability of detection failure and PAPR reduction.

Single-Event Response of the SiGe HBT Operating in Inverse-Mode

The single-event effect sensitivity of inverse-mode biased SiGe HBTs in both bulk and SOI technology platforms are investigated, for the first time, using digital circuits and stand-alone device test structures. Comparisons of heavy-ion broad beam data of shift register circuits constructed with forward-mode and inverse-mode biased SiGe HBTs from a first-generation, complementary SOI SiGe BiCMOS process, reveal an improvement in SEU mitigation for the inverse-mode shift register architecture. Full 3D TCAD simulations highlight the differences in transient current origination between forward and inverse-mode biased devices, illustrating the impact of doping profiles on ion-induced shunt duration. To extend the analysis to a bulk platform, new fourth-generation npn , SiGe HBTs were biased in both the forward and inverse-mode and irradiated at NRL using the two photon absorption measurement system. These measurements support the analysis of transient origination using 3D TCAD simulations. Furthermore, the isolation of the output terminal from the sensitive subcollector-substrate junction is experimentally demonstrated for the inverse-mode bias. Fully coupled mixed-mode simulations predict a significant reduction in sensitive area for inverse-mode shift registers built in a bulk SiGe platform.

Detection of M-Sequences from Spike Sequence in Neuronal Networks

In circuit theory, it is well known that a linear feedback shift register (LFSR) circuit generates pseudorandom bit sequences (PRBS), including an M-sequence with the maximum period of length. In this study, we tried to detect M-sequences known as a pseudorandom sequence generated by the LFSR circuit from time series patterns of stimulated action potentials. Stimulated action potentials were recorded from dissociated cultures of hippocampal neurons grown on a multielectrode array. We could find several M-sequences from a 3-stage LFSR circuit (M3). These results show the possibility of assembling LFSR circuits or its equivalent ones in a neuronal network. However, since the M3 pattern was composed of only four spike intervals, the possibility of an accidental detection was not zero. Then, we detected M-sequences from random spike sequences which were not generated from an LFSR circuit and compare the result with the number of M-sequences from the originally observed raster data. As a result, a significant difference was confirmed: a greater number of “0–1” reversed the 3-stage M-sequences occurred than would have accidentally be detected. This result suggests that some LFSR equivalent circuits are assembled in neuronal networks.

Low Energy Magnetic Domain Wall Logic in Short, Narrow, Ferromagnetic Wires

We present circuit simulation results of an implementation of universal logic that operates at low switching energy. Information is stored in the position of a single domain wall in a thin, short ferromagnetic wire. The gate is switched by current-driven domain wall motion, and information is read out using a magnetic tunnel junction. The inputs and outputs of the device are currents controlled by voltage clocks, making it compatible with CMOS. Using devices that operate at 100-1 mV, we simulate a shift register circuit and a full-adder circuit. The simulations show that the magnetic logic gates can operate at lower switching energy than CMOS electronics.

A nanowire-based shift register for display scan drivers

The development of display scan drivers is an essential step in the effort to developtransparent and flexible display devices based on nanowire transistors. Here we report atransparent nanowire-based shift register that functions as the standard logic circuit of adisplay scan driver. To form the shift register circuits using only n-type nanowiretransistors, a novel circuit structure was introduced to avoid the output voltage droptypical of purely n-type circuits. A circuit simulation based on the measured nanowiretransistor characteristics was developed in the planning phase to verify the circuitoperation of the shift register. The shift register successfully produced an output of0–3 V without an output voltage drop while applying an input of 3 V peak topeak. In addition, the shift register was designed to have multiple channels with arandomly oriented nanowire placement method to enhance the operation yield.

MILC PMOS Poly-Silicon TFT Circuits and Application in SOP

Research towards thin film circuits is one of the most attractive directions of the large-area electronics and flexible electronics. In this work, the research on TFT shift register circuit which is critical for system integration on panel (SOP) is presented. The whole circuit is composed of MILC PMOS poly-Si TFTs. The TFT device exhibited field-effect mobility of 65.21cm2/Vs, threshold voltage of -3.5V and sub-threshold swing of 0.56V/dec. Some special design considerations were adopted to improve the robustness of the circuits. The whole shift register is composed of as many as 180 stages and exhibited well performance with frame frequency from 22Hz to 220Hz at the power supply voltage of 11V. No signal attenuation and distortion appeared from the first to the final stage. The effect of bootstrapping and dynamic behavior is analyzed. The fabrication and reliability analysis are also discussed in this paper. Overall, the high performance driver circuits based on our MILC PMOS process are possible and have the potential in the application of SOP.

A single-clock-driven gate driver using p-type, low-temperature polycrystalline silicon thin-film transistors

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31″ WVGA (800×480) LCD panel, and the fabricated circuits were verified via simulations and measurements.

Single Event Transient Hardness of a New Complementary (npn <formula formulatype="inline"><tex Notation="TeX">$+$</tex></formula> pnp) SiGe HBT Technology on Thick-Film SOI

We report heavy-ion microbeam and total dose data for a new complementary (npn + pnp) SiGe on thick-film SOI technology. Measured transient waveforms from heavy-ion strikes indicate a significantly shortened single-event-induced transient current, while maintaining the total dose robustness associated with SiGe devices. Heavy-ion broad-beam data confirm a reduced single event upset (SEU) cross-section in a high-speed shift register circuit.

High speed ant colony optimization CMOS chip

Ant colony optimization (ACO) is an optimization computation inspired by the study of the ant colonies’ behavior. This paper presents design and CMOS implementation of the ant colony optimization based algorithm for solving the TSP problem. In order to implement ant colony optimization algorithm in CMOS, we will present a new algorithm. This algorithm is based on the original ant colony optimization but it can be implemented in CMOS. Briefly, pheromone matrix is transformed on the chip area and ants move up-down through the pheromone matrix and they make their decisions. Finally ants select a global path. In previous researches only pheromone values is used, but select the next city in this paper is based on heuristics value and pheromone value. In definition of problem, we use heuristics value as a matrix. Previous researches could not be used for wide type of optimization problem but our chip gives heuristics value initially and we can change initial value of heuristics value according to the optimization problem so this capability increases the flexibility of ACO chip. Simple circuit is used in blocks of our chip to increase the speed of convergence of ACO chip. We use Linear Feedback Shift Register (LSFR) circuit for random number generator in ACO chip. ACO chip has capability of solving the big TSP problem. ACO chip is simulated by HSPICE software and simulation results show the good performance of final chip.

Reference Complementary Metal–Oxide–Semiconductor Circuits and Test Structures for Evaluation of Dynamic Noise in Power Delivery Networks

A loop shift register (SR) circuit represents power noise generation of sequential logic operation in a given complementary metal–oxide–semiconductor (CMOS) technology. Reference experiments on noises over power delivery networks have been conducted in 0.18 µm 1.8 V, 90 nm 1.2 V, and 90 nm 1.0 V technologies. It is consistently shown that power and ground noises exhibit universal dependency on circuit activity and follow to equivalent circuit simulation based on capacitance charging modeling of active devices, along with static impedances derived from power delivery networks of a test structure.

Design of poly-Si TFT Shift Register and Latch Circuit by PMOS Process

The design of the PMOS dynamic shift register is proposed. This circuit had no static power consumption when generating the scan pulse output. The further research on the data driver circuit is also presented. Using PMOS dynamic shift register we had fabricated, we designed a digital signal latch unit based on PMOS TFT technology. The data signal could be sampled and latched serially through the combination of shift register and latch unit. Furthermore, we present a novel 2-phase clock shift register. It was composed of a dynamic signal transmitting part and a static signal holding part. Since the adoption of static holding circuit and the effect of bootstrapping, there is no capacitance in the schematic, which leads to a more compact and stable layout. The simulation result from Smart-Spice of Silvaco EDA software will be discussed.

The design of efficiently-encodable rate-compatible LDPC codes - [transactions papers

We present a new class of irregular low-density parity-check (LDPC) codes for moderate block lengths (up to a few thousand bits) that are well-suited for rate-compatible puncturing. The proposed codes show good performance under puncturing over a wide range of rates and are suitable for usage in incremental redundancy hybrid-automatic repeat request (ARQ) systems. In addition, these codes are linear-time encodable with simple shift-register circuits. For a block length of 1200 bits the codes outperform optimized irregular LDPC codes and extended irregular repeat-accumulate (eIRA) codes for all puncturing rates 0.6~0.9 (base code performance is almost the same) and are particularly good at high puncturing rates where good puncturing performance has been previously difficult to achieve.

Comparison of list mode data acquisition and shift register measurements using the large epithermal neutron multiplicity counter (LEMC)

Neutron multiplicity analysis has been a valuable technique for safeguards measurements of plutonium oxide and mixed oxides. Historically, most of these measurements have been performed using shift register based electronics. The shift register data acquisition lacks certain flexibility because the basic coincidence parameters (e.g., pre-delay, gate width, and long delay) must be fixed prior to the start of the measurement and the values may potentially, therefore, be sub optimal. List mode or time stamped data acquisition records the arrival time of each pulse thereby preserving the history of the pulse stream and allowing analysis and reanalysis using software analogs to the shift register circuit with adjustable parameters. Until recently, the data rates encountered in the assay of modest amounts of plutonium using efficient multiplicity counters were beyond the capacity of readily available personal computers. The calibration of the large epithermal neutron multiplicity counter (LEMC) for assay of plutonium scrap materials is used as a vehicle to compare the performance of the multiplicity shift register and a commercially available list mode acquisition module.