Abstract
The design of the PMOS dynamic shift register is proposed. This circuit had no static power consumption when generating the scan pulse output. The further research on the data driver circuit is also presented. Using PMOS dynamic shift register we had fabricated, we designed a digital signal latch unit based on PMOS TFT technology. The data signal could be sampled and latched serially through the combination of shift register and latch unit. Furthermore, we present a novel 2-phase clock shift register. It was composed of a dynamic signal transmitting part and a static signal holding part. Since the adoption of static holding circuit and the effect of bootstrapping, there is no capacitance in the schematic, which leads to a more compact and stable layout. The simulation result from Smart-Spice of Silvaco EDA software will be discussed.
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