On the way towards wide-spread flexible large-area electronics, several features are of particular interest. With focus on low-cost applications, the manufacturing requires high throughput, preferably realized by simple methods on large-area flexible substrates, for example spin coating, inkjet-printing or roll-to-roll techniques. In view of mobile applications with low power consumption, complementary logic circuit designs are beneficial; these require p-channel and n-channel field-effect transistors with large, balanced mobilities and good air stability. For low-temperature-processed p-channel transistors with mobility greater than 1 cmV s 1 and excellent air stability, a variety of conjugated organic semiconductors are available. Performance and stability of organic semiconductors for air-stable n-channel transistors have improved as well, although the largest mobilities are still below 1 cmV s . Beyond field-effect transistors, additional functionalities, such as non-volatile memory properties, are of interest, for example to individualize radio-frequency identification tags or to store user-relevant information on smart cards. Ideally, these additional features are realized with the same electronic devices that are used for the logic circuits. Inorganic semiconductors typically have large electron mobilities, but they are not usually compatible with lowtemperature solution processing. Precursor solutions of the desired inorganic material can sometimes be processed with solution techniques and then converted through thermal treatment. However, the required temperatures are often too high to be compatible with plastic substrates. Another approach utilizes nano-sized inorganic components, such as nanoparticles, nanorods or nanowires. These can be dispersed in suitable solvents and thereby processed with solution-based methods. Therefore, efforts to combine the possibility of solution processing with the superior electronic properties of inorganic semiconductors have been undertaken in recent years, using various approaches. Here, we report on air-stable n-channel thin-film transistors (TFTs) based on solution-processed zinc oxide nanoparticles (ZnO-NPs). The transistors exhibit large drain currents in combination with a tunable non-volatile hysteresis, which makes them attractive candidates for non-volatile memory transistors. Due to the low processing temperatures of 100 8C, the transistors are compatible with flexible plastic substrates. Zinc oxide was chosen as a non-toxic semiconductor with a large band gap of 3.4 eV and large electron mobility. It can be synthesized by solution-based or vapor-based methods into various types of nano-structures, ranging from nanoparticles over nanorods, nanorings, tetrapods, to nanowires. We have used a mono-disperse core-shell system with a spherical ZnO core with a diameter of about 5 nm coated with an organic ligand shell of about 1 nm thickness. The particles were provided by SusTech Darmstadt (Germany) as a stable dispersion in methyl tert-butyl ether (MTBE) (14.5 wt% of ZnO-NP). Crack-free films with uniform thickness of about 30 nm, determined by scanning electron microscopy SEM, and reproducibly small agglomerate size were obtained by spin-coating from a dilute formulation of 0.5 wt% ZnO-NPs in MTBE. The atomic force microscopy (AFM) image in Figure 1a shows a uniform film composed of individual spheres with a diameter of about 15 to 25 nm. These spheres are agglomerates of about 10 to 15 primary ZnO nanoparticles, as can be seen from the scanning tunneling microscopy (STM) image shown in Figure 1b. Films prepared from formulations with higher concentration produce significantly larger agglomerates, 300 to 400 nm in diameter, and thus films with inhomogeneous thickness. In addition, these films exhibit large cracks up to 1mm in width after drying. Formulations with a concentration of less than 0.5 wt% ZnO nanoparticles tend to dewet and leave parts of the surface uncovered, regardless of the type of substrate. Thin-film transistors were fabricated in bottom-gate (Fig. 1c) or top-gate configuration (Fig. 1d), both on glass and thermally oxidized silicon substrates. Gate electrodes and source/drain contacts were prepared by thermal evaporation of aluminum through a shadow mask. (On some substrates, gold was used for the gates.) As the gate dielectric, a 140 nm thick layer of poly(4-vinylphenol) (PVP) was deposited by spin-coating. On most substrates, the PVP was mixed with a cross-linking agent; these films were thermally cross-linked at a temperature of 200 8C. This temperature is above the glass transition temperature of polyethylene terephthalate (PET) and polyethylene naphthalate (PEN). Although this does not eliminate the possibility of realizing functional devices on such substrates, lower process temperatures are of interest. Therefore, in some top-gate devices, PVP films were also prepared without crosslinking agent and dried at 100 8C. For all devices, the semiconductor layer was deposited by spin-coating a 0.5 wt%
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Oct 6, 2011
Klaus Boldt + 3
Open Access