Shallow Trench Isolation Region Research Articles

Succeeded Foundation Effect of Stretched Gate and SiGe Array Diffusion Zones on Film-Type Strained Silicon pMOSFETs

AbstractIt has demonstrated to exploit various layout effects of advanced strained engineering to enhanced the performance of nano-scaled transistors. In actual fabrications, the gate framework usually protrudes out to the channel area even over the spuriously diffused active region, over the soft shallow trench isolation region. The foregoing device feature is interesting and critical when enhancing and managing mobility gain are taken into account by used mechanics and induced strained silicon technology in narrow scale channel widths devices. Thus, a silicon-based 22 nm p-type MOSFET combined stressors of a source/drain Si75Ge25 alloy and a -2 GPa compressive contact etch stop layer with different protrudent gate widths to investigate this issue. The fabricated oriented stress simulation extracted stress component within the device channel to estimate and analyze the performance of mobility gain and stress contours for the concerned nanoscale device.

Total Ionizing Dose Response of Different Length Devices in 0.13 μm Partially Depleted Silicon-on-Insulator Technology**Supported by the Weapon Equipment Pre-Research Foundation of China under Grant No 9140A11020114ZK34147, and the Shanghai Municipal Natural Science Foundation under Grant Nos 15ZR1447100 and 15ZR1447200.

An anomalous total dose effect that the long length device is more susceptible to total ionizing dose than the short one is observed with the partially depleted silicon-on-insulator technology. The measured results and 3D technology computer aided design simulations demonstrate that the devices with different channel lengths may exhibit an enhanced reverse short channel effect after radiation. It is ascribed to that the halo or pocket implants introduced in processes results in non-uniform channel doping profiles along the device length and trapped charges in the shallow trench isolation regions.

Effect of contact-etch-stop-layer and Si1-xGex channel mechanical properties on nano-scaled short channel NMOSFETs with dummy gate arrays

The layout effect influences the performance of nanoscale devices with advanced strain engineering, considering that the size of a technology node continuously shrinks to ≤20nm. Transistors with a long gate width could be fabricated, and the portion that protrudes outside the channel region could be located on a soft shallow trench isolation region and even across the dummy active region of diffusion. Induced strained silicon technology should be considered when managing and enhancing mobility gain in devices with narrow channel widths. Thus, we fabricated a 20nm silicon-based n-type metal-oxide-semiconductor field-effect transistor with a Si0.75Ge0.25 alloy channel and a+3.0GPa tensile contact etch stop layer as stressors. The transistor was utilized at different dummy gate arrays and dummy poly pitches. The fabricated device was subjected to oriented stress simulation, and the relationship between the piezoresistance effect and the stress component within the device channel was investigated. The best performance, which was 40% higher than that of conventional transistors, was observed in the transistor with 100nm gate width.

Study of the dose rate effect of 180 nm nMOSFETs

Radiation induced offstate leakage in the shallow trench isolation regions of SIMC 0.18 μm nMOSFETs is studied as a function of dose rate. A “true” dose rate effect (TDRE) is observed. Increased damage is observed at low dose rate (LDR) than at high dose rate (HDR) when annealing is taken into account. A new method of simulating radiation induced degradation in shallow trench isolation (STI) is presented. A comparison of radiation induced offstate leakage current in test nMOSFETs between total dose irradiation experiments and simulation results exhibits excellent agreement. The investigation results imply that the enhancement of the leakage current may be worse for the dose rate encountered in the environment of space.

A New Method for Extracting the Radiation Induced Trapped Charge Density Along the STI Sidewall in the PDSOI NMOSFETs

The effects of the radiation-induced trapped charge in shallow trench isolation (STI) and buried oxide (BOX) on total ionizing radiation response of 0.13 μm partially-depleted silicon-on-insulator (PDSOI) NMOS technology are analyzed respectively. The positive trapped charge in the STI oxide, but not in the BOX, is responsible for the off-state leakage increase after ON bias radiation. A new method is proposed to calculate the surface charge density along the STI sidewall. This method takes into account the influences of the non-uniform electric field and the variable oxide thickness in the STI region. Moreover, the calculated non-uniform charge density along the STI sidewall is verified by three dimensional simulations. Even though there is charge-accumulation in the BOX, it shows minimal impact on the front-gate characteristics of the PDSOI devices in this 0.13 μm technology, except for the device with low body doping concentration. The positive charge trapped in BOX can induce significant threshold voltage shift in the RVT (regular Vth) I/O NMOSFET through coupling effect.

Multiregion DCIV: A Sensitive Tool for Characterizing the $\hbox{Si/SiO}_{2}$ Interfaces in LDMOSFETs

By measuring the substrate current under the forward bias of source/drain-substrate junction, a multiregion direct current current-voltage (MR-DCIV) technique is used to characterize the interface trap density and location in shallow-trench-isolation (STI)-based laterally diffused metal-oxide-semiconductor devices. The interface traps in LDMOSFETs yielded sharp well-resolved peaks in MR-DCIV current spectra. The interface traps in STI region can be measured without inducing any potential damages on the gate oxide by this nondestructive characterization tool. This technique can provide not only across-wafer as-grown interface trap profile but also stress-induced defect information.

The relaxation of intrinsic compressive stress in complementary metal-oxide-semiconductor transistors by additional N ion implantation treatment with atomic force microscope-Raman stress extraction

Based on the stress extraction and measurement by atomic force microscope-Raman technique with the nanometer level space resolution, the high compressive stress about 550 MPa on the Si active region (OD) is observed for the current complementary metal-oxide-semiconductor (CMOS) transistor. During the thermal budget for the standard manufacture process of the current CMOS transistor, the difference of thermal expansion coefficients between Si and Shallow Trench Isolation (STI) oxide results in this high compressive stress in Si OD and further degrades the electron carrier mobility seriously. In order to relax this intrinsic processed compressive stress in Si OD and try to recover this performance loss, the novel process is proposed in this work in addition to the usage of one-side pad SiN layer. With this novel process of additional N-ion implantation (IMP) treatment in STI oxide, it can be found that the less compressive stress about 438 MPa in Si OD can be achieved by the smaller difference of thermal expansion coefficients between Si and N-doped SiO2 STI oxide. The formation of Si-N bonding in N-doped SiO2 STI region can be monitored by Fourier transform infrared spectroscopy spectra and thermal expansion coefficients for Si, SiO2, and SiN are 2.6 ppm/K, 0.4 ppm/K, and 2.87 ppm/K, respectively. The effective relaxation of intrinsic processed compressive stress in Si OD about 112 MPa (from 550 MPa to 438 MPa) by this proposed additional N IMP treatment contributes ∼14% electron carrier mobility enhancement/recovery. The experimental electrical data agree well with the theoretical piezoelectricity calculation for the strained-Si theory.

Low Dose Rate Effects in Shallow Trench Isolation Regions

Dose-rate effects are studied in shallow trench isolation regions. Increased damage is observed at low dose rate, with a different dose dependence compared to tests done at high dose rate. A three-dimensional modeling program was used to show that charge trapping occurs much deeper in the trench region when sufficient charge is present to reduce the field in the trench.

Reducing the influence of STI on SONOS memory through optimizing added boron implantation technology

The influence of shallow trench isolation (STI) on a 90 nm polysilicon-oxide-nitride-oxide-silicon structure non-volatile memory has been studied based on experiments. It has been found that the performance of edge memory cells adjacent to STI deteriorates remarkably. The compressive stress and boron segregation induced by STI are thought to be the main causes of this problem. In order to mitigate the STI impact, an added boron implantation in the STI region is developed as a new solution. Four kinds of boron implantation experiments have been implemented to evaluate the impact of STI on edge cells, respectively. The experimental results show that the performance of edge cells can be greatly improved through optimizing added boron implantation technology.

Study of silicon strain in shallow trench isolation

Raman spectroscopy has been used as a primary tool to measure silicon strain on shallow trench isolation (STI) test structures. Different STI dielectric gap fill materials have been evaluated as well as the effect of tensile and compressive STI liners on silicon strain. It has been shown that both intrinsic stress of thin film dielectric material and STI structure type affect strain in silicon. Ways of generating high stress in silicon are discussed including the effect of the STI chemical vapor deposition liner material on Si strain. Strain simulation data are found to be in reasonably good agreement with the active area silicon. Advantages and limitations of Raman based strain metrology in the semiconductor industry are delineated. The findings have been confirmed electrically on metal-oxide-semiconductor field effect transistor devices with tensile and compressive strains in the STI region. An improvement in p-type field-effect transistor performance has been demonstrated for silicon on insulator devices with tensile dielectric in STI.

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

In this paper, the optimization issues of various drain-extended devices are discussed for input/output applications. The mixed-signal performance, impact of process variations, and gate oxide reliability of these devices are compared. Lightly doped drain MOS (LDDMOS) was found to have a moderate performance advantage as compared to shallow trench isolation (STI) and non-STI drain-extended MOS (DeMOS) devices. Non-STI DeMOS devices have improved circuit performance but suffer from the worst gate oxide reliability. Incorporating an STI region underneath the gate-drain overlap improves the gate oxide reliability, although it degrades the mixed-signal characteristics of the device. The single-halo nature of DeMOS devices has been shown to be effective in suppressing the short-channel effects.

A model for radiation-induced off-state leakage current in N-channel metal-oxide-semiconductor transistors with shallow trench isolation

A radiation-induced leakage current model in deep submicron bulk silicon N-channel metal-oxide-semiconductor field effect transistor (NMOSFET) is proposed in this paper for circuit simulations. The model takes into account the impact of the substrate doping concentration, the angle of shallow trench isolation (STI) region, and the junction depth of source/drain, which can predict the off-state leakage current of the NMOSFET with STI region irradiated at different radiation doses. The model is verified by comparing with the experimental results. The model can be easily implemented into the circuit simulator to evaluate the impact of total ionizing dose effect on the performance of circuit.

Convergence of Hot-Carrier-Induced Saturation Region Drain Current and On-Resistance Degradation in Drain Extended MOS Transistors

Hot-carrier-induced device degradation in n-type high-voltage drain-extended MOS (DEMOS) devices stressed under high drain voltage and high gate voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vg</i> ) is investigated. Charge pumping data and technology computer-aided-design simulation results reveal that hot-carrier-induced interface state formation in the gate overlapped shallow trench isolation region is responsible for device degradation. Furthermore, an unexpected high saturation region drain current ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Id</i> (sat)) degradation (close to on-resistance degradation) is observed. The occurrence of quasi-saturation under high <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vg</i> bias is the cause of significant <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Id</i> (sat) degradation. The results presented in this paper suggest that severe <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Id</i> (sat) degradation may become a reliability concern for devices exhibiting the quasi-saturation phenomenon.

Impact of proton-radiation-induced spacer damage on the dc characteristics degradation in deep-submicron metal-oxide-semiconductor field effect transistors

The dc characteristics degradation of 0.18 μm metal-oxide-semiconductor field effect transistors (MOSFETs) after 10 MeV proton irradiation is comprehensively investigated in this paper. The measured results show that the off-state drain current is increased in N-channel MOSFETs, which is due to the turn on of the parasitic transistors induced by the shallow trench isolation regions. While in P-channel MOSFETs, the threshold voltage increase (absolute value), the transconductance degradation, and the saturation drain current decrease are observed. From the analysis, it is concluded that the basic damage mechanism is not ascribed to the gate oxide and the isolation region. The origin of the observed changes may be mainly due to the damage in the spacer oxides of the transistors. In order to verify the assumption, the leakage current passing through the spacer between the gate and the drain is measured before and after irradiation with floated source/substrate and grounded drain. We find that the leakage current is two to three times larger after irradiation. Finally, in order to confirm the extrapolation, 2-dimension (2D) simulation has been performed with Synopsys TCAD (technical computer-aided design) Sentaurus Device Simulation tools (ISE 10.0). The behavior of the simulated charges trapped in the spacers is qualitatively consistent with the experimental results.

Submicron mapping of strained silicon-on-insulator features induced

Real-space maps of strain within silicon-on-insulator (SOI) features induced by adjacent, embedded shallow-trench-isolation (STI) SiO2 regions were obtained using x-ray microbeam diffraction. The quantitative strain mapping indicated that the SOI strain was largest at the SOI/STI interface and decreased as a function of distance from this interface. An out-of-plane residual strain of approximately −31με was observed in the blanket regions of the SOI. A comparison of the depth-averaged strain distributions to the strain profiles calculated from an Eshelby inclusion model indicated an equivalent eigenstrain of −0.55% in the STI regions acting on the SOI features.

Characterization and modeling of flicker noise in junction field-effect transistor with source and drain trench isolation

The flicker or low-frequency noise behaviors of the junction field-effect transistor (JFET) with source and drain shallow trench isolation (STI) regions for planner technology are studied in detail. High noise level is found in the devices with the source and drain isolation and the normalized drain flicker noise is found to be gate bias dependent. The excess noise is identified as the surface noise generated at the oxide/Si interface in the isolation regions and a model is developed to explain the bias dependencies of the noise level and frequency index of the noise spectra. Although a larger low-frequency noise was found in the STI-JFET when compared with the conventional bulk type JFET, it is still an attractive structure for integrating into CMOS technology for low-noise analog applications. The noise level can be further minimized by keeping STI region small and using a better oxidation technique for the STI passivation.

Low dark current CMOS image sensor pixel with photodiode structure enclosed by P-well

A low dark current CMOS image sensor pixel which can be easily implemented using a standard CMOS technology without any process modification is presented. Dark current is mainly generated from the interface region between the shallow trench isolation (STI) and the active region. The proposed pixel can reduce dark current by separating the STI region from a photodiode, using a simple layout modification to enclose the photodiode junction with the P-well. A test sensor array has been fabricated using 0.18 µm standard CMOS process and its performance characterised. The dark current of the proposed pixel has been measured as 0.93fA/pixel, which is by a factor of two smaller than that of the conventional design.

Width-dependent anomalous CoSi x sheet resistance change by Ti and TiN capping process

In order to minimize the circuit propagation delay, self-aligned silicide ( salicide) technology has been widely used to reduce source/drain/gate spreading resistance and contact resistance. Cobalt silicide (CoSi 2) is the most popular silicide material beyond 0.25 μm node as it has less line width dependence than titanium silicide (TiSi 2). Cobalt on silicon with TiN capping or Ti capping has been widely applied for years and demonstrates a very promising manufacturability and scalability toward 0.1 μm and below. In this work, width-dependent sheet resistance change was studied and the anomalous sheet resistance behavior was observed to be very different for these two different capping materials. The different silicide profiles around active regions and shallow trench isolation (STI) interface were identified to be the root cause for this difference. The stress built at STI and active regions played an important role for silicide formation. Experimental results can conclude that capping material selection is very crucial for deep submicron ultralarge silicon integrated (ULSI) circuit.