Shallow Trench Isolation Process Research Articles

Computational Modeling of CMP Pads: Analyzing the Pad Geometry’s Impact on Planarization Efficiency

The pad choice has a dominant effect in polish behavior during a shallow trench isolation (STI) process. That pad must be chosen in connection with the pattern to be polished, as a pattern may consist of features that span various scales. An ideal pad will result in high planarization efficiencies across all feature sizes, in a low within-die range (strong uniformity across the die), and in low within-wafer ranges (strong uniformity across the wafer). Computational simulations make it possible to test various candidate pad designs, in search of an optimal pad design. We present our CMP modeling framework and use it to evaluate the planarization efficiency of a feature array, and the within-die range of a particular pattern, for pads with varying segment widths.The contact wear model simulates the contact between an oxide die and the polymeric polishing pad. We predict the contact pressure distribution by representing three modes of pad deformation: surface deformations due to local indentations, bulk pad segment downward displacements due to net pressures on the segments, and bulk pad rotations due to effective moments. We calculate the bulk deformations uses finite element simulations (details provided in [1]). We calculate the deformation due to local indentations using Nogi and Kato’s approach [2]. We then use the predicted pressure distribution, along with Preston’s equation, to incrementally remove oxide on the die.As discussed in [1], the pad’s surface texture has a dominant effect in contact wear simulations. Whereas [1] used theoretically generated pad surfaces, here, we use experimentally measured, used pad surfaces. Figure 1(a) shows the measured pad scan (left: the 95 mm x 77 mm overview of the concentric ring pad; right: a cross-section through the pad scan).Our experiment uses a 1.35 mm concentric ring pad, where the segments have an elastic modulus of 790 MPa and the subpad has an elastic modulus of 55 MPa. Note that for this particular pad, since the elastic modulus of the segment material is only one order of magnitude greater than the elastic modulus of the subpad, the effects of local surface indentations dominate over any bulk segment downward displacements or rotations.Modelling results (shown in Figure 1b) indicate that simulations for this pad track the experiments well. The lines represent the simulation, and the error bars represent experimental measurements (95% confidence intervals of the mean). Simulations track the experiments reasonably well. Simulations lie within the error bars for all 4 of the trench measurements, and they lie within the error bars for 3 of the 4 active measurements. Further work aims to improve this agreement.The simulations show the evolution of the die’s topography throughout the polish. Figure 1c shows the simulated die topography after 0, 25, 50, and 75 s of polish. Simulations do indeed show oxide planarization, as the within-die range decreases as the polish time increases.We use these contact simulations to evaluate neighborhood effects. For the 200 micron checkerboard array, we change the pattern density of the features directly to the right. Figure 1d shows that as the pattern density of the right neighbor increases, the material removal rate of the features being evaluated decreases. Of particular note is that the length scale over which these neighborhood effects acts is about 4 mm.We also use this model to predict the polish behavior when using different pad designs. Here, we focus on the pad ring width’s impact on the polish properties. We simulate polishes with four different ring widths: 0.35 mm, 0.45 mm, 0.70 mm, and 1.35 mm. Simulations indicate that pads with a larger ring width result in a larger planarization efficiency, compared to the smaller ring width pads. Figure 1e shows a plot of the predicted planarization efficiency versus step height for a 200 µm checkerboard array using a specific pad design. As the pad ring width is increased, simulations predict higher planarization efficiencies, as expected. Further, simulations show that pads with a larger ring width result in a smaller within-die range. Figure 1f shows a plot of the simulated within-die range versus pad ring width. The within-die range is calculated at the instance when the average active oxide thickness across the die is 100 Å. The plot shows that pad designs with a larger ring width result in a smaller within-die range, as expected.Looking forward, our die-scale model can be used to optimize pad designs and die layouts.

Radiation-tolerance analysis of I-gate n-MOSFET according to isolation oxide module in the CMOS bulk process

The n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET) produced in the widely used CMOS bulk process takes radiation damage by the total ionizing dose (TID) effects in radiation environments, so the radiation-tolerant properties of semiconductor integrated-circuits (ICs) used in high-radiation environments is a critical issue. The formation method of the isolation oxide module (IOM), which induces the radiation-induced leakage currents, differs depending on the chip density of the CMOS bulk process. In this paper, we designed and fabricated I-gate n-MOSFETs for bulk process and analyzed the radiation-tolerant characteristics according to IOM. The I-gate n-MOSFET chips are fabricated using the shallow trench isolation (STI) 0.18um and local oxidation of silicon (LOCOS) 0.35um processes of the CMOS bulk process. Tests and evaluation of the TID effects on the chips are carried out by irradiating a total cumulative dose up to 2 Mrad(Si). As the results, in the standard n-MOSFET, the leakage currents of the LOCOS and STI processes are 27.7uA and 16.4uA, and in I-gate n-MOSEFT, are 1.1uA and 0.7uA. The leakage currents of standard n-MOSFET increased by about 25 times before and after irradiation, but the electric characteristics of I-gate n-MOSFET is maintained regardless of the process. Therefore, the process versatility of the I-gate n-MOSFET with the radiation-tolerant performance has been verified.

Adjustable Silicon Corner Rounding Radius by Wet Technique

Shallow trench isolation (STI) and active area (AA) top corner rounding is important to devices performance. AA top corner rounding techniques include STI etch, linear oxidation , H2 annealing and wet oxide pull back (PB). However, conventional STI etch will caused AA facet and need to additional thermal in linear oxidation or H2 annealing processes. Wet oxide PB is easily to control the pad oxide etching amount and reach desired AA top corner top rounding radius.In this study, different pad oxide PB amount by Hydrogen Fluoride (HF) with corner rounding correlation were shown. At high pad oxide PB amount, additional hydrogen peroxide (H2O2) with dilute HF can optimize the AA top corner profile and enlarge the corner radius. Sharp AA corners profile caused gate oxide formation thickness thinning let strong electrical filed at AA corner. In wafer acceptable test had brought about double hump effect in I-V characteristics and inverse narrow width effect. Pad oxide PB following STI Etch is used by HF to let the silicon top corner be exposed and beneficial for increasing AA top corner rounding radius of liner oxidation process. This study gives some course to improve the silicon corner profile and AA top corner radius. After STI etch process, different wet etch amount were used for pad oxide PB from pad nitride by 0.49% HF process time adjustment. Different wet oxide PB amount were split for corner radius comparison. As oxide PB amount increased from 0nm to 5nm the corner radius can be improved, and the best radius showed at PB 5nm. When oxide PB amount add to 7.5nm, the corner radius became worse slightly. The radius of PB 10nm is even worse and close to without oxide PB process. This result suspected that AA corner profile might be changed in wet oxide PB process. When oxide PB amount increase, oxide etch rate might decrease and exposed silicon corner be continually damaged by HF erosion. The silicon damage of PB 5nm is slight and can be recovered after linear oxidation thermal process. At PB 7.5nm the AA corner “stepped” profile was observed. It can explain while the PB amount >5nm the corner rounding radius decrease. Because the “stepped” profile caused the corner split two curvatures then the radius decrease. The “stepped” profile of PB amount >7.5nm still be find after linear oxidation. To reduce the AA top corner “stepped” profile, the post-HF treatment’s AA silicon exposed in following APM process. The AA top corner and silicon sidewall which with APM treatment is clipping suspect H2O2 oxidize silicon and NH4OH consume the oxide caused. This profile made the region of exposed silicon to be deficient and pointed in AA geometry of silicon corner. The pointed AA top corner profile is unhelpful for corner rounding radius improvement, so the key factor of AA top rounding profile is corner silicon loss controller. In order to reduce the corner silicon loss amount, using H2O2 to replace the APM and dilute HF concentration to do oxide PB. This optimistic experience will be expected lower the exposed corner silicon consumption and corner rounding radius improvement. According oxide PB amount 5nm and 7.5nm comparison in 0.49%HF, the corner radius reduced 0.1nm when the PB increased. Nonetheless, HF concentration changed from 0.49% to 0.1% and H2O2 addition, the corner radius can be improved 0.3nm and 0.7nm. This result proved that the corner silicon profile of PB >5nm will be damaged in concentrated HF wet etch. Change to dilute HF concentration will reduce corner silicon loss and enable to recover corner silicon which with “stepped” profile by additional H2O2 treatment. As the higher oxide PB amount the pad oxide PB rate will become lower cause that without oxide protected corner silicon will be damaged and result in “stepped” profile. Nevertheless, using dilute HF can lower corner silicon loss and reduce the silicon erosion which without oxide protected. Additional H2O2 treatment introduced the rounding and smooth profile. The relationship between pad oxide PB and AA top corner rounding is established in STI process. The AA top corner radius of oxide PB amount 5nm can be improved 2.6nm compare to without PB process. When oxide PB amount >5nm the corner radius is decreased. The decreasing corner radius come from higher oxide PB amount that without oxide protected corner silicon will be damaged. This phenomenon result in “stepped” profile with difference curvature and corner radius decreasing. Dilute HF with H2O2 treatment is demonstrated that it is beneficial to reduce and recover the corner damaged. Figure 1

Radiation Hardening by the Modification of Shallow Trench Isolation Process in Partially Depleted SOI MOSFETs

Two radiation hardening processes for shallow trench isolation (STI), i.e., Si+ implantation and STI oxide nitridation are investigated, including the impact on nominal electrical characteristics and radiation hardness. The total ionizing dose effects of the nMOS devices are proved to be sensitive to the STI radiation hardening process conditions. There are optimum process conditions to achieve the best effectiveness of radiation hardening. Then, a 130-nm radiation-hardened PDSOI technology has been developed. The radiation hardness is verified by static random access memories with small storage capacities.

Super junction LDMOS with step field oxide layer

A novel step-oxide super junction-lateral double-diffused metal-oxide-semiconductor field-effect transistor (SOSJ-LDMOS) structure is proposed and optimised which allows the high breakdown voltage (BV) and low-specific on-resistance ( R on,sp ). The proposed structure overcomes the effect of thick field oxide formed by shallow trench isolation process in conventional buffer layer SJ-LDMOS ( N -buffered SJ-LDMOS), effectively enhancing the performance of the SJ-LDMOS. Thanks to the SO layer, a new electric field peak has been introduced in the surface electric field distribution, which makes the lateral surface electric field uniform in the off-state. Moreover, due to the thinner oxide layer, in the on-state the majority of electron current is accumulated near the top surface under the field plate and the thinner oxide layer also provides a wider current flowing path. In the virtue of integrated systems engineering (ISE) simulation, not only has the BV of SOSJ-LDMOS been increased, but also the R on,sp has been reduced simultaneously compared with the N -buffered SJ-LDMOS in the same drift length. In addition, when SOSJ-LDMOS and N -buffered LDMOS are at the same BV, the R on,sp of SOSJ-LDMOS is decreased by 26.3-38.9%, compared with the N -buffer SJ-LDMOS.

Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes

An experimental low-frequency noise (LFN) assessment of long channel Ge pFinFET devices fabricated in different shallow trench isolation (STI) processes is presented, taking into consideration devices with fin widths from 100 nm (planar-like) down to 20 nm. In addition, the correlation among LFN parameters, hole mobility and threshold voltage, is also evaluated. The carrier number fluctuation ( $\Delta N$ ) model is confirmed as dominant mechanism for all studied Ge pFinFETs and there is no correlation with the used STI process. From the LFN, it is evidenced that the Coulomb scattering mobility mechanism plays an important role for STI-first process, resulting in a mobility degradation.

Effect of a Multi-Step Gap-Filling Process to Improve Adhesion between Low-K Films and Metal Patterns

A multi-step deposition process for the gap-filling of submicrometer trenches using dimethyldimethoxysilane (DMDMOS), (CH3)2Si(OCH3)2, and CxHyOz by plasma enhanced chemical vapor deposition (PECVD) is presented. The multistep process consisted of pre-treatment, deposition, and post-treatment in each deposition step. We obtained low-k films with superior gap-filling properties on the trench patterns without voids or delamination. The newly developed technique for the gapfilling of submicrometer features will have a great impact on inter metal dielectric (IMD) and shallow trench isolation (STI) processes for the next generation of microelectronic devices. Moreover, this bottom up gap-fill mode is expected to be universally for other chemical vapor deposition systems.

Fluorescence Correlation Spectroscopic Studies of Particle Properties for Colloidal Ceria Abrasives Used in Chemical-Mechanical Planarization

Fluorescence correlation spectroscopy (FCS) has been demonstrated as a versatile technique for the analysis of the smallest size fraction (diameter < 20 nm) of an abrasive silica particle dispersion and for small molecule adsorption on these particles (1-3). The technique employs the adsorption of a fluorophore at an abrasive particle’s surface, followed by single-particle detection of the dye-bound abrasive particle. Subsequent evaluation of the diffusion coefficients for all fluorescent species in the abrasive dispersion enables the quantitative determination of the fraction of adsorbed and non-adsorbed dye molecules. In the present study, the FCS method is extended to the analysis of particle size distributions of smaller-sized colloidal ceria CMP abrasives and the quantitative characterization of dye adsorption on ceria particles. This application of FCS reflects the growing commercial importance of ceria-based slurries in CMP processes, such as shallow trench isolation (STI), which rely on both mechanical and chemical mechanisms in the CMP process4. Adsorption of the high quantum yield dye, Rhodamine 110 (R110), on ceria abrasive particles is shown to render the particles fluorescent for abrasives as small as 10 nm in hydrodynamic diameter. The sizing of particles in this diameter range is often problematic for a number of commonly employed techniques, such as static laser light differential centrifugal sedimentation. The FCS approach is demonstrated to have the additional advantage of being a single-particle technique which enables sizing determinations at nanomolar concentrations of fluorescently tagged ceria particle dispersions. Because dye molecules adsorb at specific sites on the particles, the technique provides a window on the surface chemistry of abrasive ceria particles. This characterization is discussed in conjunction with the FCS analysis of competitive adsorption of R110 and a widely employed CMP slurry additive, picolinic acid, which is used in STI processes. Further enhancements of the FCS technique for the characterization abrasive ceria dispersions, such as particle size distribution determination via the method of maximum entropy (MEM-FCS) and the use of the photon counting histogram (PCH) technique for the determination of molecular brightness of dye-bound particles as a metric for quantitative adsorption analysis are discussed. References Moinpour, M.; Wayman, A.; Rawat, R.; Carver, C. T.; Remsen, E. E. Surface Adsorption of CMP Slurry Additives on Abrasive Particles. ECS Trans. 2013, 52,489-494.Jacobson, L.M.; Turner, D.K.; Rawat, A.; Carver, C.T.; Tripathi, A.; Moinpour, M.; Remsen, E.E. Application of Fluorescence Correlation Spectroscopy in the Characterization of Particle Size Distributions of Colloidal Silica Abrasives Used in Chemical-Mechanical Planarization. ECS Trans. 2014, 61, 55-63.Jacobson, L.M.; Turner, D.K.; Wayman, A.; Rawat, A.; Carver, C.T..; Moinpour, M.; Remsen, E.E. Characterization of Particle Size and Surface Adsorption for SiO2 Abrasives Used in Chemical Mechanical Planarization via Fluorescence Correlation Spectroscopy. ECS J. Solid State Sci. Tech. 2015 , 4, P5053-P5057.Carter, P. W.; Johns, T. P. Interfacial Reactivity between Ceria and Silicon Dioxide and Silicon Nitride Surfaces: Organic Additive Effects. Electrochem. Solid-State Lett. 2005, 8, G218–G221.

The Effect of Amino Acids on Step Height Reduction in STI CMP

Shallow trench isolation (STI) process has been a crucial technology to isolate the transistors in ultra large scale integration (ULSI) device [1]. In STI process, step height of dielectric material is inevitably formed after gap-filling process due to the different pattern density. Chemical mechanical planarization (CMP) process has been employed to remove the step height. Remaining step height would cause defects such as dishing and erosion, therefore the reduction of step height can be considered as one of the critical issues in STI-CMP process.Several groups have studied about the step height reduction using ceria due to its high removal rate of SiO2 [2]. Lim et al. reported that the effect of particle size on step height reduction. They showed that the large particle size could improve the step height reduction by its high removal rate. Recently, the needs of small particle have been increased because the defect control has been more important as the design rule is getting narrow. Therefore, it is inevitable to develop new methodology to enhance the step height reduction. Here, we used different amino acid to modify the surface of ceria and enhance the interaction between the ceria slurry and SiO2.We investigated the effect of ceria slurries prepared with L-serine, proline, glutamine and amino butyric on step height reduction. We calculated the interaction forces between ceria with different amino acids and SiO2 film by Derjaguin-Landau-Verwey-Overbeek (DLVO) theory. The result shows that ceria slurry with L-serine or proline has higher attractive interaction forces with SiO2 than the slurry with glutamine or amino butyric acid (Fig. 1).The results of SiO2 pattern as different pattern density and line width show that the ceria slurry with L-serine or proline produces higher step height reduction than the slurry with glutamine or amino butyric (Fig. 2). As a result, we found that the high interaction forces between ceria slurry and SiO2 contribute to high step height reduction and it is stronger in case of the slurry with L-serine or proline than the slurry with glutamine and amino butyric acid.

Influence of the STI sidewall angle on the induced channel stress in nanoscaled PMOSFETs

The effect of the shallow trench isolation (STI) sidewall angle (α) on the induced channel stress and the device performance of nanoscale (32 nm, 45 nm, 90 nm gate length) p-type metal-oxide-semiconductor field-effect transistors (PMOSFETs) has been studied by using simulations. Simulation results show that STI sidewall angle improves both the channel current Id and the transconductance g m , and it does not degrade on/off current ratio I on /I off . The result is helpful to gain insight into the physical mechanisms of and to further improve sub-100 nm device performance based on STI process optimization.

A Non-Destructive and Effective Metrology to Automatically Monitor Kink Effect of MOSFETs

The kink effect is a harassed issue existing in metal-oxide-semiconductor field-effect transistors (MOSFETs) and usually degrades the whole chip performance, especially in analog circuit operation. No matter what the device isolation is with local oxidation of silicon (LOCOS) process or shallow trench isolation (STI) process, this effect more or less depicts. How to sense this effect in integrated-circuit (IC) mass-production is a crucial event. Through a second derivative method on Ids versus Vgs curves in MOSFET device, the unhealthy devices can be effectively screened out with the application of programmable auto testers. Using this derivative metrology implemented into the measurement testers, the distribution of kink devices on wafer is easily plotted. This information is very precious to the semiconductor process engineers in process improvement, too.

Enhancement of CMOSFETs Performance by Utilizing SACVD-Based Shallow Trench Isolation for the 40-nm Node and Beyond

This paper reports an improved densification anneal process for sub-atmospheric chemical vapor deposition (SACVD)-based shallow trench isolation (STI) to enhance CMOSFETs performance for 40-nm node and beyond. The improved STI densification process is demonstrated to generate a lower compressive stress in the active area as compared to the Standard STI process used in 40 nm technology. For nMOS devices with the improved densification process, the reduction of STI compressive stress is beneficial to the electron mobility and leads to an enhancement of on-current (ION ). In addition, the ION enhancements would significantly increase with shrinking the device dimensions (gate width and source/drain length). On the other hand, the improved densification process would not degrade the pMOSFET's performance resulting from the very small piezoresistance coefficients for 〈1 0 0〉 channel direction. The superior junction leakage characteristics for the junction diodes with the improved anneal process can further verify the lower STI-induced compressive stress due to the less energy bandgap narrowing. Hence, the improved STI process can be adopted in 40-nm CMOS technology and beyond, where device structures have very small active areas.

Impact of Reducing Shallow Trench Isolation Mechanical Stress on Active Length for 40 nm n-Type Metal–Oxide–Semiconductor Field-Effect Transistors

We report an improved densification annealing process for sub atmospheric chemical vapor deposition (SACVD)-based shallow trench isolation (STI) to enhance n-type metal–oxide–semiconductor field-effect transistor (nMOSFET) performance for 40 nm node and beyond. Experimental results show that this improved STI densification process leads to lower compressive stress in the small active area compared with the standard STI process. This is beneficial to electron mobility and leads to an enhancement of on-current (ION). Moreover, comparable drain induced barrier lowering (DIBL) and subthreshold swing (SS) characteristics for both devices indicate that the improved densification process would no significant influences on process variations or dopant diffusions. Hence, the improved STI process can be adopted in 40 nm complementary metal–oxide–semiconductor (CMOS) technology and beyond.

Simultaneous Etching and Deposition Processes during the Etching of Silicon with a Cl2/O2/Ar Inductively Coupled Plasma

AbstractIn this article, surface processes occurring during the etching of Si with a Cl2/O2/Ar plasma are investigated by means of experiments and modeling. Cl2‐based plasmas are commonly used to etch silicon, while a small fraction of O2 is added to protect the sidewalls from lateral etching during the shallow trench isolation process. When the oxygen fraction exceeds a critical value, the wafer surface process changes from an etching regime to a deposition regime, drastically reducing the etch rate. This effect is commonly referred to as the etch stop phenomenon. To gain better understanding of this mechanism, the oxygen fraction is varied in the gas mixture and special attention is paid to the effects of oxygen and of the redeposition of non‐volatile etched species on the overall etch/deposition process. It is found that, when the O2 flow is increased, the etch process changes from successful etching to the formation of a rough surface, and eventually to the actual growth of an oxide layer which completely blocks the etching of the underlying Si. The size of this etch stop island was found to increase as a function of oxygen flow, while its thickness was dependent on the amount of Si etched. This suggests that the growth of the oxide layer mainly depends on the redeposition of non‐volatile etch products. The abrupt change in the etch rate as a function of oxygen fraction was not found back in the oxygen content of the plasma, suggesting the competitive nature between oxidation and chlorination at the wafer. Finally, the wafer and reactor wall compositions were investigated by modeling and it was found that the surface rapidly consisted mainly of SiO2 when the O2 flow was increased above about 15 sccm. magnified image

NMOS Narrow Width Devices Drive Current Improvements through STI Processes and Channel Implantation Optimization

NMOS narrow width transistor driving current as a function of shallow trench isolation (STI) processes and channel implant conditions were studied on a 65nm CMOS technology. It is found that the magnitude of compressive stress in STI could modulate the trend of NMOS drive current versus width dependence that was attributed to channel dose profile uneven distribution under the influence of stress. It is seen that the channel body effect factor (gamma) of large width (W=10um) transistor is smaller than that of narrow width device (W=0.12um). This difference increases as STI compressive stress scales up. The phenomena are consistent with the analysis that Boron dose distribution varies as STI stress changes. it is shown that the down trend of drive current for narrow width transistors could be minimized by STI process optimization, or by introducing indium implantation during channel implantation processes.

Evaluation of Stress and Crystal Quality in Si During Shallow Trench Isolation by UV-Raman Spectroscopy

Defects and stress gradually accumulate throughout various Si large-scale integration fabrication processes. It is essential to monitor defects and stress carefully to suppress their unintentional introduction. In this study, we measured the stress and crystal quality in shallow trench isolation (STI) samples by ultraviolet (UV)-Raman spectroscopy with an extremely high-resolution wavenumber to evaluate the effect of post-annealing on the recovery of Si crystals. The variations of crystal quality in 200-mm wafers with STI structures gradually decreased after post-annealing for 4 h, 6 h, and 8 h; however, there was no substantial difference in the values of full-width at half-maximum of the Raman spectra. Precise measurements of variations of stress and crystal quality were successfully performed by UV-Raman spectroscopy with a high-resolution wavenumber, which enabled us to evaluate the STI process accurately.

Shallow trench isolation stress modification by optimal shallow trench isolation process for sub-65-nm low power complementary metal oxide semiconductor technology

Shallow trench isolation (STI) induced mechanical stress affects the device behavior in the advanced complementary metal oxide semiconductor (CMOS) technology. This article presents how to use an optimal STI process to reduce transistor mismatch and leakage current induced standby current in static random access memory (SRAM). The STI induced mechanical stress affects the device behavior in the advanced CMOS technology. The optimized STI process can reduce junction and bulk leakage that occurs on the STI sidewall due to STI compressive stress enhancing boron diffusion and increasing junction electric field of STI sidewall resulting in band-to-band-tunneling (BTBT) degradation. An obvious decrease in BTBT occurs on STI edge sidewall that is observed by using the optimized STI process. Meanwhile, the optimized STI process has better length of diffusion effect. Moreover, the optimized STI process can improve the parasitic device at STI edge because of smaller divot. Since random fluctuation of channel dopant and process induced device mismatch are major considerations in SRAM cell, we examine STI sidewall boron dopant diffusion effect on SRAM due to BTBT increasing exponentially with increasing doping concentration in the P-well of negative metal oxide semiconductor field effect transistor. The mismatch of passing gate of SRAM and Vcc_min can also be improved by leakage reduction from the optimized STI process due to improved random dopant fluctuation.

Selective Chemical Mechanical Polishing of Silicon Dioxide over Silicon Nitride for Shallow Trench Isolation Using Ceria Slurries

For the shallow trench isolation process, in which a thin silicon nitride film acts as a polish stop layer, a polishing slurry with a high oxide to nitride removal rate selectivity is required to remove the overburden oxide. In this work, we show that using ceria-based slurries and only 0.05% of any one of three different cyclic amine additives, namely, pyridine HCl, piperazine, and imidazole, very low nitride (<2 to 3 nm/min) and high oxide (∼350 nm/min) removal rates can be obtained for blanket films. The role of these additives in the slurry toward achieving the desired removal rate selectivities of silicon dioxide over silicon nitride is discussed considering pyridine HCl as an example, using zeta potential, contact angle, adsorption isotherm, and thermogravimetric analysis data.

Gate oxide wear out using novel polysilazane-base inorganic as nano-scaling shallow trench filling

The phenomenon of floating gate (FG) crystallization and extrinsic gate oxide breakdown ( V bd) are discussed using polysilazane-base inorganic material SOD (Spin-On-Dielectric) as shallow trench isolation (STI) filling for 50 nm flash memory fabrication. The pinholes are found along the FG grain boundary in wide active regions because of tensile stress induced by SOD material in STI process, thus gate oxide wears out by following wet cleaning steps. The chemical oxide formation during FG deposition can effectively inhibit gate oxide early breakdown. Moreover, FG sheet resistance ( R s) in 550 °C/air deposition condition can significantly reduce about 20% in comparison with 520 °C/O 2 and 400 °C/N 2 conditions.

High-resolution X-ray diffraction as a tool to investigate the evolution of local stress in sub-micrometric Si lines isolated by periodic arrays of oxide-filled trenches

The periodic strain induced in mono-crystalline Si lines isolated by the Shallow Trench Isolation process is investigated by High-Resolution X-ray diffraction which is very sensitive to local strain and is non-destructive. The array periodicity gives rise to satellites in the reciprocal space around the Si Bragg peak, their envelope being directly linked to the local strain field. In the particular case of sub-micrometric arrays, the reciprocal space maps present a secondary diffraction peak caused by a homogeneous strain area in the middle of the Si lines. The secondary intensity relative position can be translated in transverse and perpendicular strain values, which allows a quantitative comparison of samples. We first compare two process flows to show the effect of top-layer deposition on Si strain. Then, the influence of geometrical variations is studied for the softer process. When considering a fixed period, the strain is getting higher for a lower Si line/SiO 2 trench width ratio. The trenches depths variation shows a few effects on the strain values; the decrease in strain with decrease in depth is only noticeable for the transverse value. Finally, the homogeneous strain values increase with decrease in period from 580 nm down to 200 nm. All these results confirm that most of the stress is applied to the Si-active areas by the trenches filled with SiO 2.