Shallow Trench Isolation Edge Research Articles

The effect of hydrogen on programmed threshold-voltage distribution in NAND flash memories

This paper, for the first time, presents a comprehensive study into the effect of hydrogen concentration in the forming gas on the reliability of NAND Flash memories. It is newly observed that a higher hydrogen concentration leads to broaden the threshold-voltage (VT) distribution after programming. This suggests that a higher hydrogen concentration makes a larger amount of ionized hydrogens (H+) exist in the shallow trench isolation (STI), which results in the fluctuation of the Fowler–Nordheim tunneling current during programming. It is also found that the VT distribution width difference between higher and lower hydrogen concentration turns out to be smaller after the program/erase cycling. This could be explained by the neutralization of H+ due to the capture of the tunneling electrons at the STI edge. On the other hand, the higher hydrogen concentration proves to be able to provide better retention characteristics. Thus, the programming and retention characteristics are the tradeoff relationship. Therefore, optimization of the hydrogen concentration is crucial for the NAND Flash process integration.

Effects of shallow trench isolation on low frequency noise characteristics of source-follower transistors in CMOS image sensors

The effects of the shallow trench isolation (STI) edge on low frequency noise characteristics of source-follower (SF) transistors in CMOS image sensors (CIS) were investigated. Random telegraph signal (RTS) noise and 1/f noise were measured in a CIS operating voltage region for a realistic assessment. SF transistor with STI edge in contact with channel shows a lower probability of generating RTS noise but greater RTS amplitude due to the enhanced trap density induced by STI-induced damage. SF MOSFETs without STI exhibit a much lower 1/f noise power spectral density in spite of the greater RTS generation probability, which is due to the decreased trap density. Therefore, SF transistors without STI edge in contact with channel are promising candidates for low noise CIS applications.

Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

We enhance the capability of industry standard compact model BSIM6 to model the parasitic current $ I_{{\text {edge}}}$ at the shallow trench isolation edge. Accurate, efficient, and scalable model for $ I_{{\text {edge}}}$ is developed by finding the key differences between $ I_{{\text {edge}}}$ and main device drain current ( $ I_{{\text {main}}}$ ). It is found that $ I_{{\text {edge}}}$ has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to $ I_{{\text {main}}}$ . These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.

Low Temperature Atomically Flattening of Si Surface of Shallow Trench Isolation Pattern

Atomically flattening of semiconductor/gate insulator interface has received much attention for complementary metal oxide semiconductor (CMOS) devices, because such smooth interface can increase field effect mobility by reducing interface roughness scattering of carriers [1,2], improve gate insulator reliability [3] and reduce amplitudes of low frequency noise such as 1/f noise and random telegraph noise (RTN) [3,4]. Because these improvements of CMOS device performances can be obtained independent of device miniaturization, the atomically flattening technology becomes increasingly important as the device miniaturization approaches its physical limit. Atomically flat Si surface having atomic terraces and steps is known to be obtained by Ar or Ar/H2 annealing at temperature of 1100 ºC or higher [5]. However, such high temperature annealing leads to the reaction between Si and SiO2 [6], and thus, is not adequate to device fabrications where the device isolation pattern with thick SiO2 film exists on Si wafer. To introduce the atomically flattening technology to the existing CMOS process, low temperature atomically flattening Ar annealing has been developed, where flattening temperature could be decreased down to 850ºC or less by reducing O2 and H2O residue gases down to less than 30 ppb [7]. Recently, we reported that by introducing this low temperature Ar annealing at 850ºC, atomically flat Si surfaces of shallow trench isolation (STI)-patterned wafers was obtained, and not only the gate oxide reliability was improved, but also the RTN amplitude was reduced in nMOS transistors [4]. In this report, relating to the results obtained in Ref. 4, the atomically flattening effect of Si surface of device active patterns having STI edge was investigated in more detail. Figs 1(a)-1(c) show atomic force spectroscopy (AFM) images of the Si surface of large active region (p-well, 500mm × 600mm), where (a) the controlled sample (without Ar annealing), (b) the sample with Ar annealing at 900 ºC and that at (c) 850 ºC are shown. The images were obtained just after the atomic flattening Ar annealing which was applied to the samples having STI pattern. Atomically flat Si surface was successfully obtained for 850 ºC annealing, while that was not obtained for 900 ºC annealing. The results suggest that, in the case of 900 ºC annealing, O2 and/or H2O were emitted from the SiO2 film and reacted with Si surface, degrading flattening effect. The results suggested the importance of lowering of annealing temperature to obtain atomically flat Si surface when SiO2 film exists on the wafer. Relatively smaller active areas with a size of 1.26mm × 3.03mm were also measured. Figs 2(a) – 2(c) shows bird’s eye views of isolation patterns obtained by AFM for (a) the controlled sample, (b) the sample with Ar annealing at 900 ºC and that at (c) 850 ºC. Also, Figs 2(d) – 2(f) shows the AFM images of Si surface of the inside of these active areas for (d) the controlled sample, (e) the sample with Ar annealing at 900 ºC and that at (f) 850 ºC. It was found from bird’s eye’s views that the shape anomaly at the active edge was not observed, demonstrating the advantage of the low temperature annealing which can suppress reaction between Si and isolation SiO2film. Furthermore, in the case of 850 ºC annealing, atomically flat surface could be obtained. The surface roughness at the atomic terrace was the same level as the noise level (approximately 0.04 nm), while that was 0.07 nm for 900 ºC annealing and 0.13 nm for the controlled sample. The results demonstrated that the proposed low temperature and high purity atomically flattening Ar annealing is applicable to the existing CMOS process. [1] S.Takagi et al., IEEE Trans. Electron Devices, 41 (1994) 2357. [2] C. H. Lee et al., Tech. Dig., IEDM (2013) 13-32. [3] R. Kuroda et al., IEEE Trans. Electron Devices, 56 (2009) 291. [4] T. Goto et al., Extended s of SSDM2014 (2014) 670. [5] Y. Matsushita et al., ECS Trans. 3 (2006) 159. [6] R. Tromp et al., Phys. Rev. Lett. 55 (1985) 2332. [7] X. Li et al., ECS Trans. 28 (2010) 299. Figure 1

Low Temperature Atomically Flattening of Si Surface of Shallow Trench Isolation Pattern

Low temperature (800 ºC - 900 ºC) Ar annealing for atomically flattening was applied to shallow trench isolation (STI)-patterned wafers where Si and SiO2 coexist on the wafer surface. During the Ar annealing, concentrations of H2O and O2 residual gases in the annealing ambience was maintained at low level less than 30 ppb. Such low temperature and clean Ar ambience can suppress oxidation and etching of Si surface as well as a decomposition of thick SiO2 film for device isolation. As a result, the atomically flat Si surface was obtained for the Si active pattern having STI edge by the Ar annealing at 800 ºC - 900 ºC. Owing to the introduction of the atomically flat Si/gate oxide interface, breakdown characteristic of the fabricated MOS capacitors was improved for the atomically flat devices.

STI edge effect on the series resistance of CMOS Schottky barrier diodes

An analysis of the shallow trench isolation (STI) edge effect on CMOS Schottky barrier diode (SBD) is reported in this article. The STI edge effect, which includes the impact of the fringing electric field and the nonplanar intersection of STI, significantly distorts the performance of SBDs with a small junction. Due to this effect, when an array SBD is formed by connecting several SBDs with a small junction in parallel, the series resistance of the array SBD is not reduced as expected. Therefore, the cut-off frequency of an array SBD with a small unit junction SBD degenerates quickly. This phenomenon is observed in measurements of fabricated CMOS SBD prototypes. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:932–935, 2014

Investigation of STI edge effect on programming disturb in localized charge trapping SONOS flash memory cells

Abstracts The impact of shallow trench isolation (STI) on non-volatile memories has become much more serious for sub-90-nm CMOS technologies. This paper uses the localized charge trapping polysilicon-oxide-nitride-oxide-silicon (SONOS) flash memory cells to investigate STI edge effect on programming disturb when the channel hot electron injection programming method is applied. The different programming disturbs between the central cells far from STI and the edge cells close to STI are experimentally presented on the array level. At the programmed state, the edge cells suffer larger decrease of threshold voltage compared to the central cells under the same drain disturb. However, both edge and central cells at the erased state have not any significant variations of threshold voltage distribution under the same disturb conditions. In addition, both edge and central cells demonstrate almost the same behaviors under gate disturb. Two-dimension process simulation results show that the edge cells suffer a higher compressive stress caused from STI corner than the central cells. The higher compressive stress increases hole mobility, which is mainly responsible for the relatively serious drain disturb in the programmed edge cells.

Layout-Dependent Stress Effect on High-Frequency Characteristics and Flicker Noise in Multifinger and Donut MOSFETs

The impact of MOSFET layout-dependent stress on high-frequency performance and flicker noise has been investigated. The proposed donut MOSFETs demonstrate the advantages over the standard multifinger MOSFETs, such as the lower flicker noise <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$S_{\rm ID}/I_{\rm DS}^{2}$</tex></formula> in the low-frequency domain and the higher cutoff frequency <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$f_{T}$</tex></formula> in the very high-frequency region. The elimination of the transverse stress <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$ \sigma_{\perp}$</tex></formula> from shallow trench isolation (STI) and the suppression of interface traps along the STI edge are proposed as the primary factors responsible for the enhancement of the effective mobility <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu_{\rm eff}$</tex></formula> , as well as <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX"> $f_{T}$</tex></formula> , and the reduction of flicker noise. The significantly lower flicker noise realized by donut devices suggests the reduction of STI-generated traps and the suppression of mobility fluctuation due to eliminated transverse stress. The former is applied to n-channel MOS in which the flicker noise is determined by the number-fluctuation model. The latter is responsible for p-channel MOS whose flicker noise is dominated by the mobility-fluctuation model.

Shallow trench isolation stress modification by optimal shallow trench isolation process for sub-65-nm low power complementary metal oxide semiconductor technology

Shallow trench isolation (STI) induced mechanical stress affects the device behavior in the advanced complementary metal oxide semiconductor (CMOS) technology. This article presents how to use an optimal STI process to reduce transistor mismatch and leakage current induced standby current in static random access memory (SRAM). The STI induced mechanical stress affects the device behavior in the advanced CMOS technology. The optimized STI process can reduce junction and bulk leakage that occurs on the STI sidewall due to STI compressive stress enhancing boron diffusion and increasing junction electric field of STI sidewall resulting in band-to-band-tunneling (BTBT) degradation. An obvious decrease in BTBT occurs on STI edge sidewall that is observed by using the optimized STI process. Meanwhile, the optimized STI process has better length of diffusion effect. Moreover, the optimized STI process can improve the parasitic device at STI edge because of smaller divot. Since random fluctuation of channel dopant and process induced device mismatch are major considerations in SRAM cell, we examine STI sidewall boron dopant diffusion effect on SRAM due to BTBT increasing exponentially with increasing doping concentration in the P-well of negative metal oxide semiconductor field effect transistor. The mismatch of passing gate of SRAM and Vcc_min can also be improved by leakage reduction from the optimized STI process due to improved random dopant fluctuation.

Speckle Defect by Dark Leakage Current in Nitride Stringer at the Edge of Shallow Trench Isolation for CMOS Image Sensors

The leakage current in a CMOS image sensor (CIS) can have various origins. Leakage current investigations have focused on such things as cobalt-salicide, source and drain scheme, and shallow trench isolation (STI) profile. However, there have been few papers examining the effects on leakage current of nitride stringers that are formed by gate sidewall etching. So this study reports the results of a series of experiments on the effects of a nitride stringer on real display images. Different step heights were fabricated during a STI chemical mechanical polishing process to form different nitride stringer sizes, arsenic and boron were implanted in each fabricated photodiode, and the doping density profiles were analyzed. Electrons that moved onto the silicon surface caused the dark leakage current, which in turn brought up the speckle defect on the display image in the CIS.

An Investigation on Anomalous Hot-Carrier-Induced On-Resistance Reduction in n-Type LDMOS Transistors

In this paper, on-resistance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) degradation induced by hot-carrier injection in n-type lateral diffused metal-oxide-semiconductor transistors with shallow trench isolation (STI) in the drift region is investigated. <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> unexpectedly decreases under medium- and high-gate voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> ) stress conditions. According to experimental data and technology computer-aided-design simulation results, the mechanisms responsible for anomalous <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> shift are proposed. When the device is stressed under medium <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> , hot-hole injection and trapping occur at the STI edge closest to the channel, resulting in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> reduction. Interface trap generation (¿ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) occurs at the STI edge closest to the channel and nearby drift region, leading to <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> increase. For the device stressed under high <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> reduction is also attributed to hole trapping at the STI corner closest to the channel. ¿ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> created by hot-electron injection at the STI edge closest to the drain dominates device characteristics and leads to <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> increase eventually. Based on the proposed <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> degradation mechanisms, an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> degradation model is discussed and verified with experimental data.

Mechanism and Modeling of On-Resistance Degradation in n-Type Lateral Diffused Metal–Oxide–Semiconductor Transistors

In this study, on-resistance (Ron) degradation induced by hot-carrier injection in n-type lateral diffused metal–oxide–semiconductor transistors with shallow trench isolation (STI) in the drift region is investigated. Ron unexpectedly decreases at the beginning of stress, although Ron increases as the stress time becomes longer. Experimental data and results of technology computer-aided-design simulations reveal that hot-hole injection and trapping at the STI corner closest to the channel is responsible for the Ron reduction. The damage caused by hot-electron injection at the STI edge closest to the drain is responsible for the Ron increase. An Ron degradation model including the effect of hole trapping and interface trap generation is also discussed and verified with experimental data.

Investigation on the Initial Hot-Carrier Injection in P-LDMOS Transistors With Shallow Trench Isolation Structure

In this paper, early-stage hot-electron generation is shown to inject electrons into the shallow trench isolation (STI) edge above the drift region that causes the linear-region drain current to increase abruptly in the first moment of the stress for P-LDMOS transistors. After this early-stage carrier trapping, the transistor exhibits normal hot-carrier degradation during the following stress period. To further study this phenomenon, the geometry and the doping profile of the drift region near the STI edge and the polysilicon gate doping area are changed to investigate the initial IDLIN increase. Two-dimensional device simulator is used to analyze the experimental results. It is proven that the amount of current increase strongly depends on the distance from the maximum impact ionization generation rate point to the STI.

Effect of STI stress on leakage and Vccmin of a sub-65 nm node low-power SRAM

In the paper, for the first time, the effects of shallow trench isolation (STI) stress enhanced boron diffusion on band-to-band (BTBT) leakage and Vccmin of a 65 nm node low-power SRAM are investigated in detail. High temperature oxidation in the STI process induces an elastic stress to enhance the diffusion of boron dopants, thus leading to a significant increase in BTBT on the STI edge sidewall. The enhanced boron diffusion is more serious for a shorter and/or narrower device, thus worsening the mismatch of the threshold voltage and Vccmin of the devices in a 65 nm node SRAM cell significantly.

The Effect of Field Oxide Recess on Cell $V_{\rm TH}$ Distribution of nand Flash Cell Arrays

We present our study on the effect of field oxide recess on cell-programming-speed uniformity of nand flash cell memory. Due to the short distance between the control gate and the shallow-trench-isolation (STI) edge, the control-gate voltage generates uniform distribution of an electric field on the STI edge and provides strong immunity to fabrication process variation in cell programming. Therefore, the optimized field oxide recess offers an inherently narrower cell <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> distribution, fastening multilevel-cell programming speed while minimizing the floating-gate interference. Experimental results on 63-nm cell arrays show that the cell <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> distribution is reduced by 18% or more as field oxide recess increases.

On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors With STI in the Drift Region

In this letter, on-resistance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) degradation induced by hot-carrier injection in n-type lateral DMOS transistors with shallow-trench isolation (STI) in the drift region is investigated. <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> decreases at the beginning of stress, but <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> increases as the stress time is increased. Experimental data and technology computer-aided-design simulation results reveal that hot-hole injection and trapping at the STI corner closest to the channel are responsible for the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> reduction. The damage caused by hot-electron injection at the STI edge closest to the drain is responsible for the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> increase.

Real-space strain mapping of SOI features using microbeam X-ray diffraction

Synchrotron-based X-ray microbeam measurements were performed on silicon-on-insulator (SOI) features strained by adjacent shallow-trench isolation (STI). Strain engineering in microelectronic technology represents an important aspect of the enhancement in complementary metal-oxide semiconductor device performance. Because of the complexity of the composite geometry associated with microelectronic circuitry, characterization of the strained Si devices at a submicron resolution is necessary to verify the expected strain distributions. The interaction region of the SOI strain extended the SOI film thickness from the STI edge at least 25 times. Regions of 65-nm-thick SOI less than 3 μm wide exhibited an overlap in the strain fields because of the surrounding STI. Microbeam mapping of arrays containing submicron SOI features and embedded STI structures revealed the largest out-of-plane strains because of the close proximity of superimposed strain distributions induced by the STI.

Suppression of Oxide Encroachment into Floating Gate by Shallow Trench Isolation Recess in an Electrically Erasable Programmable Read Only Memory Cell

In this paper, we investigate the effects of the oxide recess in shallow trench isolation (STI) on the characteristics of electrically erasable programmable read only memory (EEPROM) cell with in situ-doped floating gate. It is found that the distribution of the program threshold voltage is improved with increasing of the oxide recess in STI. Transmission electron microscopy analysis shows that the oxide recess in STI results in the decrease of oxide thickness at the edge of STI and in the center of tunnel oxide. Also, it is observed that erase cell current is increased about 11% with oxide recess of and 21% with oxide recess of , respectively. Endurance measurements in the EERPROM cell reveal that both electron and charge generation increase with increasing recess depth when the cycling time exceeds about .

Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics

Active-area layout dependence of MOSFET parametric characteristics and its reduction by reducing shallow trench isolation (STI)-induced mechanical stress were investigated. Threshold voltages (V/sub th/) and saturation drain currents (I/sub ds/) become sensitive to the active-area layout of MOSFET in scaled-down technology. This phenomenon is the effect of mechanical stress from STI edge, which reduces impurity diffusion in channel region and enhances carrier mobility. To reduce the STI-induced stress, we examined STI-wall-oxide nitridation and STI gap-fill-oxide densifying in pure N/sub 2/ ambient. These processes reduced the reoxidation of the STI wall oxide, therefore reduced the STI-induced stress. According to the new STI process, the active-area layout dependence of V/sub th/ and I/sub ds/ were reduced successfully.

Impact of the interaction between nitrogen implant and NO anneal on narrow-width transistors

This study reports a new behavior in narrow-width transistors resulting from the interaction of oxides grown with nitrogen implant with the nitridation associated with growing other oxides. Nitric oxide (NO) annealing of 28-/spl Aring/ oxides grown on nitrogen-implanted silicon results in the decrease of NMOS threshold voltage and in the increase (absolute value) of PMOS threshold with decreasing width. This effect arises from the positive charge from NO anneal interacting with the parasitic transistor associated with the shallow trench isolation edge recess. The parasitic impact becomes more pronounced for narrower widths due to higher effect of recess on total transistor width.