Shallow Trench Isolation Research Articles

The effect of amino acid addition in CeO2-based slurry on SiO2/Si3N4 CMP: Removal rate selectivity, morphology, and mechanism research

The continuous reduction in feature size of integrated circuits has raised stricter material removal selectivity and surface quality requirements for the chemical mechanical polishing (CMP) process of shallow trench isolation (STI). To reduce surface defects, small-sized CeO2 abrasives are introduced into the CMP of STI. We investigated the impacts of three amino acids and their composites added to a 50 nm-sized CeO2 dispersion (pH maintained at 5) on the polishing of silicon dioxide and silicon nitride. The promoting or inhibitory effects of amino acids first increased and then decreased with increasing concentration. When 0.02 M lysine and 0.02 M glutamic acid were added to 0.5 wt% CeO2 dispersion, the best effect was achieved. At this time, the material removal rate (MRR) of SiO2 and Si3N4 were 2993.4 Å/min and 137.2 Å/min, respectively, with surface roughness of 0.108 nm and 0.142 nm in the 5 μm × 5 μm region. This study shows that amino acids promote the MRR of SiO2 primarily by enhancing the reactivity of Ce4+ by complexing with carboxyl groups. In contrast, amino acids inhibit the MRR of Si3N4 primarily by forming strong hydrogen bonds between the amino group and its surface, resulting in surface adsorption and suppressing the hydrolysis reaction. The CMP mechanisms of the three amino acids are similar, and the differences in their effects are mainly due to the varying numbers of amino and carboxyl groups they carry. The adsorption of three amino acids on SiO2 and Si3N4 surfaces was simulated by Materials Studio software, and the results were consistent with the experimental results. Finally, this paper explained the mechanism of action of amino acids at the microscopic level and provided some guidance on improving the performance of CeO2 slurry.

(Dielectric Science and Technology Poster Award, 2nd Place) Activation of Amine Chemistries for the Enhanced Particle Removal Efficiency of CeO2 Nanoparticles Via Megasonic Processing Conditions

With the persistent advancement of semiconductor technology, the demand for high-efficiency device manufacturing processes has surged. Chemical Mechanical Planarization (CMP) is a cornerstone for achieving angstrom-scale surface uniformity crucial for integrated circuits (IC) and logic devices. Shallow Trench Isolation (STI) CMP involves the selective removal of bulk oxide to electrically isolate active components on wafer surfaces. The modulation of the Ce3+ to Ce4+ surface state is essential for improved performance in both CMP and post-CMP (p-CMP) applications. Ce3+ is ideal for oxide material polishing due to its strong adherence to oxide surfaces, while Ce4+ is optimal for p-CMP cleaning, given its weak bond to oxide surfaces. Current p-CMP industry-standard methods utilize mechanical approaches, such as polyvinyl alcohol (PVA) brush scrubbing. However, this process induces high levels of shear force (SF), leading to secondary defects on the wafer surface (i.e. scratches, corrosion, increased surface roughness). To address these limitations, non-contact cleaning methods utilizing megasonic energy have emerged, which rely on generating reactive oxygen species (ROS) to induce particle removal. Thus, this study focuses on enhancing ceria particle removal during post-CMP cleaning by employing amine-based chemistries coupled with megasonic energy. While preliminary results imply that the mechanical cavitations induced by megasonic waves improve cleaning efficiency, this method will be optimized via the introduction of amine-based chemistries. Specifically, this work aims to leverage the unique properties of amines coupled with megasonic energy to facilitate enhanced ceria removal through electron donation, inducing a reduction in the oxidation state of ceria from Ce³⁺ to Ce⁴⁺. This approach improves particle removal while limiting secondary defects, enhancing redox activity induced by megasonic waves and chemical interactions. The mechanisms behind this method will be validated with CeO2 oxidation state kinetics, interfacial frictional changes, wafer surface roughness analysis, and SEM validation of particle removal efficiency.

CMP: Four Decades of Innovation and a Promising Future

The invention of CMP by IBM in 1983 represents an inflection point in the evolution of semiconductors. It was a bold and risky idea to mechanically apply abrasives to the surface of a wafer, but this new process for restoring a wafer to a planar state was the key to continued areal scaling and increased device complexity. Initially applied to a simple application for filling trenches with insulator, the potential of this technique was evident. Through understanding of material properties and subsequent manipulation of slurry chemistry, CMP was applied to enable the more challenging and technically critical processes for Shallow Trench Isolation and Tungsten contacts. The late 1990’s saw the introduction of copper interconnects. IBM was first to market this technology which continues to support conductors down to lines widths on the order of 10 nanometers! The CMP process required for copper interconnects demanded a thorough understanding of the materials present and potential surface phenomena for exploitation. For this need, a new and complex mechanism for copper planarization was invented. Equally challenging was the need for a subsequent non-selective barrier removal step. For this a unique, self-balancing approach was also invented, borrowing some elements from previous STI technology. Device architecture has progressed from planar geometry to FINFETs to Gate All Around, or Nanosheet technology. This evolution has required increasingly more CMP process steps with a concurrent demand for increased process control. Gate height control for Nanosheeets is currently paramount for performance, affected by many CMP steps in the process flow. A typical requirement is less than 1nm added variability per CMP step! Looking forward, CMP continues to be tapped to enable technology evolution. Polish steps are becoming part of the patterning process to enable pitch splitting for upcoming nodes. A VTFET integration approach can enable further area scaling but presents integration challenges; CMP is being asked to enable “third color” schemes for the protection of NFET vs PFET devices which is necessary at various points in the in the VTFET process flow. Heterogeneous Integration is demanding nanometer control of topography across large contact pads and large lateral distances. Finally, extreme scaling is creating fundamental challenges for metal polish at the contact and interconnect levels. CMP tool architecture currently does not provide for control of ambient conditions at the wafer surface during wet transport and post CMP cleaning. Subsequently, unwanted metal dissolution is observed. New tool designs will be needed to control wafer surface conditions, and particularly oxygen exposure through all steps within the CMP tool. This talk is dedicated to the special session in honor of Professor S.V. Babu

Effects of co-60 gamma-ray irradiation on the DC and RF characteristics of SiGe HBTs

This study investigates the effects of Co-60 gamma-ray irradiation on the DC and RF characteristics of the SiGe HBTs, with a total dose of up to 4000 krad(Si). The degradation of the forward base current is primarily attributed to surface recombination due to the induced interface traps. The ideality factor of the forward excess base current is affected by the positive oxide-trapped charges at the interface of the emitter-base spacer oxide. TCAD simulation results indicate that the effective integral region of the surface recombination rate is associated with the positive oxide-trapped charge density. The accumulation of positive oxide-trapped charges in the shallow trench isolation oxide has an impact on the potentials of the interface and epi-collector region, subsequently affecting the base diffusion current. Therefore, the ideality factor of the reverse excess base current depends on the device geometry. The RF characterization suggests that the depletion capacitance of the base-emitter junction is more susceptible to gamma-ray irradiation compared to the base-collector junction. And the cut-off frequency experiences a slight degradation as the total dose increases.

Shallow Trench Isolation Patterning to Improve Photon Detection Probability of Single-Photon Avalanche Diodes Integrated in FD-SOI CMOS Technology

The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip level. In our study, a nanostructurated layer created by an optimized arrangement of Shallow Trench Isolation (STI) above the photosensitive zone generates constructive interferences and consequently an increase in the light sensitivity in the frontside illumination. A simulation methodology is presented that couples electrical and optical data in order to optimize the STI trenches (size and period) and to estimate the Photon Detection Probability (PDP) gain. Then, a test chip was designed, manufactured, and characterized, demonstrating the PDP improvement due to the STI nanostructuring while maintaining a comparable Dark Count Rate (DCR).

Effects of Gas-Dissolved Water for Ceria Nanoparticles on the SiO2 Film Surface in Post-CMP Cleaning

As a trend of using colloidal and smaller ceria nanoparticles (CNPs) at the shallow trench isolation (STI) chemical mechanical polishing (CMP) in semiconductor manufacturing, post-CMP cleaning challenges in the removal of residual CNPs on the SiO2 film surface became much more challenging. We investigated the reduction/oxidation of ceria nanoparticles (CNPs) by hydrogen gas-dissolved water (H2 GDW), carbon dioxide gas-dissolved water (CO2 GDW), and oxygen gas-dissolved water (O2 GDW). The concentration of Ce3+ on the CNPs changed from 18.64% to 19.48%, 20.31% to 21.94%, and 21.27% to 19.22%, respectively, after immersion in H2 GDW, CO2 GDW, and O2 GDW for 3 to 12 h. Following the Ce3+ concentration of the CNP surface, adhesion energies between CNPs immersed in H2 GDW, CO2 GDW, and O2 GDW for 6 h with SiO2 surface were 6.06E-16 J, 6.18E-16 J, and 4.83E-16 J. Cleaning experiments under megasonic conditions revealed the efficacy of H2 GDW and O2 GDW in removing residual CNPs from SiO2 surfaces. The residual cerium (Ce) ion concentrations remaining on the SiO2 film surface after cleaning, were 0.06, 0.41, and 0.10 ppb for H2 GDW, CO2 GDW, and O2 GDW, respectively.

Strain visualization using large-angle convergent-beam electron diffraction

In this study, we report a strain visualization method using large-angle convergent-beam electron diffraction (LACBED).11large-angle convergent-beam electron diffraction (LACBED); scanning transmission electron microscopy (STEM); nanobeam electron diffraction (NBD); personal computer (PC); diffraction pattern (DP); transmission electron microscopy (TEM); convergent beam electron diffraction (CBED); four-dimensional (4D); gigabytes (GB); region of interest (ROI); Gatan Microscopy Suite (GMS); selected area (SA); focused ion beam (FIB); embedded SiGe (eSiGe); complementary metal-oxide semiconductor (CMOS); full width at half maximum (FWHM); cross-correlation (CC); shallow trench isolations (STIs). We compare the proposed method with the strain maps acquired via STEM-NBD, a combination of scanning transmission electron microscopy (STEM) and nanobeam electron diffraction (NBD). Although STEM-NBD can precisely measure the lattice parameters, it requires a large amount of data and personal computer (PC) resources to obtain a two-dimensional strain map. Deficiency lines in the transmitted disk of LACBED reflect the crystalline structure information and move, curve, or disappear in the deformed area. Properly setting the optical conditions makes it possible to acquire real-space images over a broad area in conjunction with deficiency lines on the transmitted disk. The proposed method acquires images by changing the relative position between the specimen and the deficiency line and can grasp the strain information with a small number of images. In addition, the proposed method does not require high-resolution images. It can reduce the required PC memory or storage consumption in comparison with that of STEM-NBD, which requires a high-resolution diffraction pattern (DP) from each point of the region of interest. Compared with the two-dimensional maps of LACBED and NBD, NBD could detect large distortions in the area where the deficiency line curved, moved, or disappeared. The curving or moving direction of the deficiency line is qualitatively consistent with the NBD results. If quantitative strain values are not essential, strain visualization using LACBED can be considered an effective technique. We believe that the strain information of a sample can be obtained effectively using both methods.

Mitigating WL-to-WL Disturbance in Dynamic Random-Access Memory (DRAM) through Adopted Spherical Shallow Trench Isolation with Silicon Nitride Layer in the Buried Channel Array Transistor (BCAT)

The Pass Gate Effect (PGE), often referred to as adjacent cell interference, presents a significant challenge in dynamic random-access memory (DRAM). In this study, we investigate the impact of PGE and propose innovative solutions to address this issue in DRAM technology, employing 10 nm node technology with buried channel array transistors. To evaluate the efficacy of our proposals, we utilized SILVACO for simulating various DRAM configurations. Our approach centers on two key structural optimizations: the introduction of a spherical Shallow Trench Isolation (STI) and the incorporation of a silicon nitride (Si3N4) layer within the spherical STI structure. These optimizations were meticulously designed to mitigate the PGE by considering several factors that are highly influential in its manifestation. To validate our approach, we conducted comprehensive simulations, comparing the PGE factors of typical DRAM structures with those of our proposed configurations. The results of our analysis strongly support the effectiveness of our proposed structural enhancements in alleviating the PGE when contrasted with conventional DRAM structures. Remarkably, our optimizations achieved a remarkable 82.4% reduction in the PGE, marking a significant breakthrough in the field of DRAM technology. By addressing the PGE challenge and substantially reducing its impact, our research contributes to the advancement of DRAM technology, offering practical solutions to enhance data integrity and reliability in the era of 10 nm node DRAM.

Effect of Proton Irradiation on Complementary Metal Oxide Semiconductor (CMOS) Single-Photon Avalanche Diodes

The effects of proton irradiation on CMOS Single-Photon Avalanche Diodes (SPADs) are investigated in this article. The I–V characteristics, dark count rate (DCR), and photon detection probability (PDP) of the CMOS SPADs were measured under 30 MeV and 52 MeV proton irradiations. Two types of SPAD, with and without shallow trench isolation (STI), were designed. According to the experimental results, the leakage current, breakdown voltage, and PDP did not change after irradiation at a DDD of 2.82 × 108 MeV/g, but the DCR increased significantly at five different higher voltages. The DCR increased by 506 cps at an excess voltage of 2 V and 10,846 cps at 10 V after 30 MeV proton irradiation. A γ irradiation was conducted with a TID of 10 krad (Si). The DCR after the γ irradiation increased from 256 cps to 336 cps at an excess voltage of 10 V. The comparison of the DCR after proton and γ-ray irradiation with two structures of SPAD indicates that the major increase in the DCR was due to the depletion region defects caused by proton displacement damage rather than the Si-SiO2 interface trap generated by ionization.

Radiation-Induced Charge Trapping in Shallow Trench Isolations of FinFETs

Radiation-Induced Charge Trapping in Shallow Trench Isolations of FinFETs

Stimuli-Responsive CeO2 Removal Via Surface Redox Modulation during Shallow Trench Isolation (STI) Post-Chemical Mechanical Planarization (p-CMP)

As transistor miniaturization continues to extend Moore’s Law into the future of technology, the demand for high-efficiency device manufacturing processes has increased drastically in recent years. More specifically, a critical step in preparing integrated circuits (ICs) and logic devices is Chemical Mechanical Planarization (CMP), which relies on a delicate balance of chemical and mechanical parameters to achieve angstrom-level surface uniformity and ultimately allows for increased transistor packing density. A sub-area of CMP that has gained significant attention is Shallow Trench Isolation (STI), which involves the isolation of electrically active components by removing the bulk oxide (i.e., tetraethyl orthosilicate (TEOS)) overburden from the deposition process. During polishing, chemical slurries comprised of CeO2 nanoparticles, rate enhancers, selectivity and rheology modifiers, and pH adjusters are utilized to activate the oxide layer and consequently remove material. The STI removal mechanism, known as the chemical tooth model, involves the nucleophilic attack of CeO2 nanoparticles at surface defect states (i.e., oxygen vacancies (Ovacs)) and resultant dative Ce-O-Si bond formation, which makes the surface redox state of CeO2 (i.e., Ce3+/Ce4+) a key driver for oxide-nanoparticle interactions. It is well known that Ce3+ nanoparticles contain a higher concentration of Ovacs, which enhances the material removal rate (MRR). However, the hard adsorption properties of CeO2 have resulted in the demand for a more efficient post-CMP (p-CMP) cleaning process for TEOS that promotes increased CeO2 removal without inducing secondary defects (i.e., scratching, dishing, corrosion, etc.). Current industry-standard methods involve using a polyvinyl alcohol (PVA) brush to transport harsh chemistries to contaminated surfaces under high shear force (SF). Additionally, the use of megasonic energy is an emerging non-contact cleaning mode that relies on generating reactive oxygen species (ROS) (i.e., cavitations) to induce particle removal. Previous work has shown that supramolecular additives improve overall particle removal efficiency (PRE) when implemented in traditional PVA brush cleaning due to their ability to encapsulate and charge-flip CeO2 nanoparticles while reducing SF. As a result, this research investigates a combinatorial approach to PVA brush cleaning utilizing megasonic energy to release Fenton catalysts from polymer capsules, which aid in the production of ROS through H2O2 decomposition. Initial results have shown that, by increasing the concentration of ROS during cleaning, a Ce3+ à Ce4+ transition occurs on the surface of adsorbed CeO2, enhancing overall PRE.

Release of Redox Additives Via Megasonic Energy for High Selectivity/Low-Stress STI CMP

The advancements in a wide array of semiconductor manufacturing processing have been pivotal for the extension of Moore’s law the Chemical Mechanical Planarization (CMP) process has become an area of focus due to the stringent surface topography requirements. CMP utilizes complex slurry formulations containing abrasive nanoparticles and additives to reduce substrate defectivity and achieve angstrom-level uniformity. One area that has gained significant attention is Shallow Trench Isolation (STI), where the modulation and control of the surface oxidation state of the ceria, specifically the Ce3+ state, is critical to TEOS removal. In the Ce3+ state, defect states (i.e., oxygen vacancies (Ovacs)) on the surface are highly electron deficient (i.e., electrophilic) and allow the nucleophilic substrate to complex. By modulating the electrophilic properties of the particle, the kinetics of surface complexations required for effective TEOS removal can be controlled. This work focuses on developing stimuli-responsive capsules that can be added to STI slurry formulations to promote the controlled release of redox-active additives that can be used to drive the oxidation state of the CeO2 nanoparticle (Ce3+/Ce4+). By encapsulating the additive in a polymeric system, the reactive properties of the slurry are limited until the additive is released. In this work, megasonic action was employed to disrupt the capsules releasing the additives on demand to facilitate the modulation of the CeO2 surface redox states. Results have shown that the addition of a controlled-release capsule with an additive resulted in the increase of Ovacs at the CeO2 surface. This led to an increase from 1800 Å/min to 3450 Å/min using a constant 2.0 W/cm2 continuous flow megasonic flux. Furthermore, the overall defectivity decreased significantly with respect to both particle contamination and surface scratching. Lastly, the nature of the polymeric capsule has been shown to enhance selectivity between TEOS and silicon nitride and preliminarily appears to be megasonic flux dependent.

Impact of Oxygen on the Generation of Slip Lines and the Electronic Properties of Si-based Substrates

The impact of oxygen in silicon substrates and the formation of oxide precipitates have been widely investigated in the past, because of deleterious electrical recombination and their impact on yield [1]. The presence of oxygen can also be beneficial, with the so-called internal gettering effect by oxygen precipitates. More recently, researchers pointed out the role of interstitial oxygen on the formation of slip lines and dislocations [1-2]. The impact of interstitial oxygen during thermal treatments has to be distinguished from the one of oxygen precipitates for a better understanding of various phenomena [3]. We show in this paper the combined impact of features such as interstitial oxygen, thermal processes and innovating SOI substrates on slip-line generation after complex device fabrication process flows.We have investigated different kinds of silicon and SOI substrates (with silicon obtained with the Czochralski method) that were submitted to different thermal treatments during a specific 65nm process flow targeting Radio-Frequency devices. We have worked on 300mm patterned and blanket wafers and focused notably on a last stressing oxidizing anneal step used for gate oxide formation. One type of SOI substrates had a poly-silicon layer beneath the buried oxide (named SOI Trap-Rich) specifically for RF applications [4]. We have used two kinds of processes, low and high temperature, in Rapid Thermal Oxidation (RTO) tools. Slip-line counts and cumulated lengths were monitored on blanket SOI and Si wafers after main anneal steps and gate oxide RTO, using a Pattern Wafer Geometry (PWG) tool (figure 1). The post-nitridation anneal for gate oxide formation was performed at temperature above 1000°C in single wafer tools. On Si and SOI with 70nm-thick Si layers, no slip-lines were detected using Process-Of-Record conditions (whatever the process temperature). Meanwhile, high temperatures and above all extreme edge offset temperatures (usually used in single wafer reactors to have processes as uniform as possible) resulted in higher slip-line counts and cumulated lengths on the wafers back-sides. On SOI with TR layers, slip-lines were detected whatever the conditions, although they were less numerous with a low temperature and optimized process.Differences for wafers processed at the same time highlighted the influence of several parameters: the thermal history evidenced by wafer-to-wafer variability for SOI wafers with a Trap-rich layer underneath, the stack (SOI type and nature) and the process temperature used during previous oxidation steps. A typical map obtained by the PWG is shown in Figure 2 [5]. Meanwhile, Figure 3 shows a macro Photoluminescence mapping of a blanket Silicon wafer, pointing out the electrical activity of planar defects at the wafer edges (non-radiative recombination on dislocations). A direct relationship was found between the slip-line origin and contact points coming from ring supports at wafers’ back-side (the origins of slip lines). Figure 4 shows the relationship between the oxygen concentration in bulk Si and the silicon handles of SOI substrates, the slip-line counts and wafer warp. Based on this trend, we have also statistically confirmed on patterned wafers processed in a 65nm RF flow, the direct relationship between substrate deformation, low oxygen concentration in the Si handle (lower at wafer edge in agreement with slip line formation) and lithography overlay (OVL) measurements. When OVL exceeded a certain value, residuals (i.e. misalignments due to shifts between patterns which are symbolized by vectors) could not be corrected any more. It is typically what we have on SOI TR substrates with an extreme offset temperature (intentionally too high). An OVL signature out of our range of specifications is shown in Figure 5 on a patterned wafer processed up to gate oxide level. High numbers of slip lines result in OVL over detection. Meanwhile, wafer deformations and more precisely stresses that are too high increase OVL residuals. Above a given threshold, the built-in stress in the wafer is so high that slip lines are nucleated at the wafer edges to minimize the elastic energy. Above a second threshold, the wafer deformation is irreversible. Finally, the relationship between OVL and electrical failure is not straightforward and more often the consequence of mixed parameters such as substrate composition and nature, annealing steps and etching during Shallow Trench Isolation or gate oxide definition.[1] J. Fujise et al, Japanese J. of Applied Physics, 57 (035501) 2018[2] J. Fujise et al, J. Solid State Science and Techn., 9 (055012) 2020[3] G. Kissinger et al, J. Solid State Science and Techn., 8 (N79) 2019[4] B.K. Esfeh et al, Solid State Electronics, 128 (121) 2017[5] V. Brouzet et al, ASMC conference, april 2019 Figure 1

Restricted hydrolysis reaction of Si3N4 via nonionic polymer adsorption in advanced shallow trench isolation chemical mechanical planarization

The adoption of ultra-fine nanoparticles as an abrasive has garnered notable attention in shallow trench isolation (STI) chemical mechanical planarization (CMP) due to its potential in scratch reduction. However, the poor removal rate, attributed to the physicochemical interaction between abrasive and conventional organic passivation agent, limits the introduction of ultra-fine nanoparticles. Here, a nonionic polymer polyvinyl alcohol (PVA), without particle interaction, is proposed as a novel passivation agent to restrict the hydrolysis reaction of Si3N4 film in the advanced STI CMP process. The selective adsorption of PVA onto the Si3N4 film lowers its removal rate by suppressing the hydrolysis reaction via hydrogen bonding while the removal rate of SiO2 film remains constant. Moreover, the uniformity of SiO2 removal is improved due to the enhanced fluidity of slurry, resulting from increased wettability between pad and slurry. As a result, the removal selectivity between both films has been improved to 113.4:1 and the in-wafer-uniformity (IWU) of SiO2 film is supplemented by 96.8 % simultaneously.

The role of ammonium citrate and dodecyl pyridinium chloride on chemical mechanical polishing relevant to SiO2 dielectric layer

Silicon dioxide films are widely utilized in integrated circuit manufacturing for their excellent properties, including applications in shallow trench isolation and interlayer dielectrics. Chemical mechanical polishing (CMP) has a pivotal part in achieving material planarization across integrated circuit manufacturing process. This study delves into the mechanisms of ammonium citrate and dodecyl pyridinium chloride in the CMP of silicon dioxide dielectric layers, alongside optimizing the concentration ratios of the slurry components. The incorporation of ammonium citrate effectively mitigates electrostatic repulsion between the abrasive and the wafer surface, thereby augmenting the mechanical interactions during polishing. The introduction of dodecyl pyridinium chloride further enhances material removal rates while concurrently reducing surface roughness. Notably, employing the slurry with the optimized composition ratios yields a notable reduction in surface defects after CMP. Extensive characterization techniques, including X-ray photoelectron spectroscopy and scanning electron microscope, were devoted to elucidate the mechanisms of the additives and assess the stability of the slurry. This study substantiates that the incorporation of ammonium citrate and dodecyl pyridinium chloride in the slurry not only sustains a high material removal rate but also achieves superior outcomes in terms of lower wafer surface roughness and diminished wafer surface defects.

Effect of ionic surfactants on shallow trench isolation for chemical mechanical polishing using ceria-based slurries

Effect of ionic surfactants on shallow trench isolation for chemical mechanical polishing using ceria-based slurries

Enhancing ceria slurry performance for shallow trench isolation chemical mechanical polishing through non-ionic surfactant addition

Enhancing ceria slurry performance for shallow trench isolation chemical mechanical polishing through non-ionic surfactant addition

Reduction of the Pass Gate Effect with a Spherical Shallow Trench Isolation in the BCAT Structure

Reduction of the Pass Gate Effect with a Spherical Shallow Trench Isolation in the BCAT Structure

Effect of Total Dose Irradiation on Parasitic BJT in 130 nm PDSOI MOSFETs.

In this work, the effects of total dose irradiation on the parasitic bipolar junction transistor (BTJ) in 130 nm PDSOI MOSFETs were investigated. The experimental results demonstrate that irradiation-induced oxide-trap charges can modify the E-B junction barrier, and thereby make the common-emitter gain β0 of the parasitic BJT in NMOS device increase, while decreasing it in a PMOS device. Additionally, irradiation-generated oxide-trap charges in shallow trench isolation (STI) elevate the surface electrostatic potential of the gate above the STI sidewall, thus providing an additional channel from the emitter to the collector. Moreover, these charges may generate parasitic reverse conductive paths at the STI/Si interface under high dose irradiation, thereby enhancing the leakage current in the front gate channel and diminishing the significance of the parasitic BJT. Under irradiation, the electric field intensity difference between two biases leads to higher β0 of the parasitic BJT in PG-biased devices than in ON-biased ones. Furthermore, the lifting effect of irradiation on β0 increases in wide or short channel irradiated devices, which can be explained using simulations and an emitter current crowding effect model.

Process optimization for shallow trench isolation etch using computational models

The critical dimensions of advanced semiconductor manufacturing processes have decreased to a few tens of nanometers while the aspect ratios have increased beyond 100. The performance of plasma etch patterning processes as well as the cost and time of the development cycle are critical to the success of ramping a new technology node toward profitable high-volume manufacturing. In this paper, a computational patterning software, ProETCH®, has been developed with rigorous physics and advanced algorithms for modeling the etch patterning process, with the featured capabilities in calibrating the reaction mechanisms and optimizing the etch process. A shallow trench isolation etch process using self-aligned double patterning was investigated. A reaction mechanism of silicon etch by Ar/Cl2 plasma was developed to address the surface reactions, and a plasma hypermodel was introduced to correlate process operating conditions to plasma parameters at the wafer surface. The parameters of the reaction mechanism and the plasma hypermodel were calibrated with experimental data obtained from cross-sectional scanning electron microscope (XSEM) images. The calibrated model is used to identify the different fundamental pathways that contribute to the observed profile metrics in XSEMs. The model was then used for process development and optimization by solving the forward and inverse problems. In the forward problem, the model is used to predict the etching profile at different process conditions. Predictions for both interpolation conditions (process parameters within the range used for developing the model) and extrapolation conditions (process parameters outside of the range used for developing the model) agree well with the experimental data with the root mean square error less than 4 nm (1 nm resolution used for the mesh). In the inverse problem, the developed model is used to search for process conditions (e.g., values of bias power and pressure), which could result in desirable profiles. The solutions to the inverse problem demonstrate a degeneracy in process space of the etching process for a given target profile.