SFQ Logic Circuits Research Articles

Braiding Operations for a Topological Josephson Junction Array Using a Bipolar Current Pulse Generator Controlled by SFQ Logic Circuits

Braiding Operations for a Topological Josephson Junction Array Using a Bipolar Current Pulse Generator Controlled by SFQ Logic Circuits

A two-step routing method with wire length budgeting for PTL routing of SFQ logic circuits

A PTL routing method for large-scale SFQ logic circuits is proposed. In this method, a routing problem is solved in two steps; global routing and detailed routing. In the global routing, a routing region is split into rectangular subregions and paths connecting them are obtained. Wire length budgeting is introduced into the global routing for allocating sufficient amount of routing resources to each net considering wire length matching in the detailed routing. In the detailed routing, exact wiring routes are determined based on a solution of the global routing and wire length matching is performed at each subregion. The global routing with wire length budgeting is formulated and an algorithm for it is proposed. In the proposed global routing algorithm, initial routes are searched at first using the rip-up and reroute technique, and then, routing resource distribution is calculated by constructing a flow-graph and solving a max-flow problem. If distribution of routing resources fails, global route extension is conducted to allocate additional routing resources to nets. The routing resource distribution and the global route extension are repeated until sufficient resources are allocated to all nets. As a design example, a 16 bit Sklansky adder was designed using the proposed method. Wire length matching in detailed routing was succeeded and the target frequency of 50 GHz was achieved.

An Integrated Row-Based Cell Placement and Interconnect Synthesis Tool for Large SFQ Logic Circuits

This paper presents a row-based design methodology covering cell placement, clock tree synthesis, and routing steps for large SFQ circuits. The proposed placement tool initiates by running a state-of-the-art CMOS placer, which places fixed-height but variable-width cells in rows on the chip. Cells in each row are then grouped together such that each group contains at most $k$ cells with the same logic level. Next, for clock routing, this paper proposes HL-tree, which adopts an H-tree with passive transmission line connections to distribute the clock to groups, and within each group, a linear path composed of splitters and Josephson transmission lines (JTLs) provides the clock to cells. Increasing $k$ reduces the chip area, but also may incur a performance loss. To evaluate the effectiveness of the proposed approach, place-and-route results of a 32-bit Kogge–Stone adder for different values of $k$ are reported. By using this new design methodology, the overall chip area can be reduced by 27% compared with the results of a conventional CMOS placement accompanied by an H-tree clock network.

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits

In this paper, we propose a method for layout-driven skewed clock tree synthesis for SFQ logic circuits. For a given logic circuit without a clock tree, our algorithm outputs a circuit with a synthesized clock tree and timing adjustments achieving the given clock period and a rough placement of the clocked gates. In the proposed algorithm, clocked gates are grouped into levels and the clock tree is synthesized for each level. For each level, we estimate the clock timing for all possible placements of each gate, and then we search a placement of all gates that minimizes the total number of delay elements for timing adjustment. Once the placement is obtained, we synthesize a clock tree without wire intersections. We applied the proposed method to a moderate size circuit and confirmed that clock trees satisfying given timing requirements can be synthesized automatically.

Improvement of time resolution of the double-oscillator time-to-digital converter using SFQ circuits

We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range in addition to the high resolution and the high sensitivity of the SFQ TDC compared to semiconductor TDCs. The time resolution of the proposed TDC is limited by the resolution of the CD. In order to improve the resolution, we have developed a dynamic AND (DAND) gate, which can detect two simultaneous SFQ signal inputs with high accuracy. It was demonstrated that the time resolution of the TDC using the DAND gate is improved to be ±4ps.

Fabrication and operation of HTS SFQ logic circuits

High-temperature superconducting (HTS) single flux quantum logic circuits such as an inverter and an OR gate were designed. Circuit parameters were optimized for the HTS circuits to be successfully operated. The test circuits were fabricated by using the ramp-edge junction technology, and their logic operations were examined. The inverter was successfully operated at temperatures from 4.2K to 33K, and finite operating margins were observed in this temperature range. We also confirmed correct operation of the OR gate with dc supply current margins at temperatures from 40K to 50K.

A New Design Methodology for Single-Flux-Quantum (SFQ) Logic Circuits Using Passive-Transmission-Line (PTL) Wiring

The introduction of passive-transmission-line (PTL) wiring to large-scale SFQ logic circuits offers several advantages over traditional Josephson-transmission-line (JTL) wiring, such as smaller wiring area, less delay, lower power consumption, and more freedom in routing. PTL wiring can drastically change the style of designing SFQ logic circuits. We propose a new methodology for designing large-scale SFQ circuits using PTL wiring. Aiming at generalizing SFQ circuit design, we chose synchronous clocking. We developed a placer that was suitable for SFQ circuit design to assist us with the new design methodology. The placer first synthesizes an H-tree clock distribution network, placing SFQ pulse splitter cells at each branch. It then places logic cells to minimize the maximum length of data PTL wires, aiming at higher operating speeds. Finally, a router completes the PTL wiring. To evaluate the design methodology we designed an 8-bit general purpose RISC processor. Within twelve hours, we obtained a 15-mm-square SFQ circuit that could operate up to 27.6 GHz. We adopted an advanced Nb process, which was characterized by a critical current density of 10 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , two 5-mum-wide PTL wiring layers, and a minimum cell size of 30 mum times 30 mum. The circuit consisted of about 20,000 logic cells, which approximated more than 400,000 Josephson junctions including splitters to distribute the clock signal.

A new design approach for control circuits of pipelined single-flux-quantum microprocessors

A novel method of design for controllers of pipelined microprocessors usingsingle-flux-quantum (SFQ) logic has been proposed. The proposed design approach is basedon one hot encoding and is very suitable for designing a finite state machine using SFQlogic circuits, where each internal state of the microprocessor is represented by a flip-flop.In this approach, decoding of the internal state can be performed instantaneously, incontrast to the case in the conventional method using a binary state register. Moreover,pipelining is effectively implemented without increasing the circuit size because no pipelineregisters are required in the one hot encoding. By using this method, we have designeda controller for our new SFQ microprocessors, which employs pipelining. Thenumber of Josephson junctions of the newly designed controller is 1067, while theprevious version without pipelining contains 1721 Josephson junctions. Theseresults indicate that the proposed design approach is very effective for pipelinedSFQ microprocessors. We have implemented a new controller using the NEC2.5 kA cm−2 Nb standard process and confirmed its correct operation experimentally.

Design and implementation of double oscillator time-to-digital converter using SFQ logic circuits

We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range. The time resolution of the proposed TDC is limited by the resolution of the CD, which is about 10ps because it is made by an NDRO cell in this study. The circuits are implemented using NEC 2.5kA/cm2 Nb standard process and the CONNECT cell library. We have demonstrated the measurement of the propagation delay of a Josephson transmission line by the TDC with the time resolution of about 10ps.

Design and Implementation of Stochastic Neurosystem Using SFQ Logic Circuits

We propose a stochastic neurosystem using SFQ logic circuits and design the main components with the following functions: carrying out the multiplication of an input to a neuron on a synaptic weight value, integrating pulses to generate a membrane potential, and generating the output of a neuron. We simulate some circuits by JSIM and confirm their correct operation. We compare two methods of multipliers: using a comparator and using a divider. The multiplication using the divider is effective with respect to integration, and reduces the accumulation time N/sub a/ required for higher precision operations. We designed a 4-bit up/down counter assuming the NEC 2.5 kA/cm/sup 2/ Nb/AlO/sub X//Nb standard process. We show that it is possible to compose the activation function circuit using a comparator.

Superconducting digital electronics

Single-flux quantum logic (SFQ) circuits, in which a flux quantum is used as an information carrier, have the possibility for opening the door to a new digital system operated at over 100-GHz clock frequency at extremely low power dissipation. The SFQ logic system is a so-called pulse logic, which is completely different from the level logic for semiconductors like CMOS, so circuit design technologies for SFQ logic circuits have to be newly developed. Recently, much progress in basic technologies for designing SFQ circuits and operating circuits at high speeds has been made. With advances in these design tools, large-scale circuits including more than several thousand junctions can be easily operated with the clock frequency of more than several tens of gigahertz. High-end routers and high-end computers are possible applications of SFQ logic circuits because of their high throughput nature and the low power dissipation of SFQ logic. In this paper, recent advances of SFQ circuit design technologies and recent developments of switches for high-end routers and microprocessors for high-end computers that are considered possible applications for SFQ logic will be described.

Cell based design methodology for BDD SFQ logic circuits: A high speed test and feasibility for large scale circuit applications

We have proposed a cell-based design methodology for SFQ logic circuits based on a binary decision diagram (BDD) and implemented a BDD SFQ standard cell library using a Hypres Nb process. In this design methodology, any logic function can be implemented by connecting binary switches. Since the circuits are dual rail logic and do not need a global clock, difficulty in the timing design is reduced considerably. In our cell-based design approach, the cell library is composed of only five kinds of basic cells, whose circuit parameters are optimized so as to remove the inter-cell interaction. At the layout level, the cells have the identical size so that circuits can be implemented by simply embedding the basic cells. In this study we have performed an on-chip high-speed test of the BDD SFQ logic circuits. The test system consists of two four-bit data-driven self-timed (DDST) shift registers with a ladder type clock generator. We have confirmed 12 GHz operations of the BDD SFQ logic circuit. We have also examined circuit size dependence of the DC bias margin of large BDD SFQ circuits.

SFQ data processing with set/reset information

We propose a new class of SFQ logic circuits. In this new approach, an SFQ pulse represents the transition between zero and one. By using these two bits of information, a one-to-one correspondence between input and output can be realized. Since the correspondence is then the same as in semiconductor circuits, this method permits logic design without clock elements. In order to carry out this logic, we propose the most fundamental element, a new DC/SFQ converter. A computer simulation and low-speed test were performed. Both results showed that this converter operates correctly with a wide margin. Moreover, this converter also provides the basis for many other logic elements such as AND, OR, and XOR.

Operation of high- Tc SFQ devices at near liquid nitrogen temperature

As the operating temperature of the SFQ logic circuits gets higher by using high- T c superconductors, the effect of noise on switching a Josephson junction to the voltage state becomes more important. In this paper, we report our work on high- T c SFQ RS flip-flop which was made with YBCO thin film deposited on a SrTiO 3 bi-crystal. The circuit operated correctly at 71 K over the 200 computer-generated clock cycles without making errors, where a reset or a set operation was made over one clock cycle. Good agreement between the measured data and the calculation based on the thermal activation theory was obtained. The effective noise temperature used to fit the data was much higher than the physical temperature. This could be due to the instrument noise. Improvement in the measurement set-up might reduce the effective noise temperature. Also our measurement results indicate that the elevation of the operating temperature near the liquid nitrogen temperature may not affect the margin of the circuit.

4.6 GHz SFQ shift register and SFQ pseudorandom bit sequence generator

Superconductive electronics can provide low power, GHz speed spread spectrum satellite communications. The key components to construct the spread spectrum modem are an analog filter and a digital pseudorandom bit sequence generator, Various SFQ logic circuits are required to construct a code generator. These circuits include a shift register, a reset switch, and an XOR or XNOR. To make a 4 bit 15 sequence code generator, a four stage shift register with a fan-out of two on each stage was designed. These circuits, fabricated with eight level Nb/AlO/sub x//Nb Josephson junction integrated circuit process, showed correct operation at low speed digital tests. The low speed digital test was done by using a "catcher", the combination of a read SQUID and a Josephson transmission line (JTL) which were magnetically coupled to each other. High speed testing of the shift register used a latch amplifier, which amplified an SFQ pulse to a latching output voltage of about 2 mV. This test showed correct operation of the shift register at speeds of up to 4.6 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>