Set Of Subfunctions Research Articles

MASA: An efficient framework for anomaly detection in multi-attributed networks

Anomalous connected subgraph detection has been widely used in multiple scenarios, such as botnet detection, fraud detection and event detection. Nevertheless, the huge search space makes a serious computational challenge. Moreover, the anomalous connected subgraph detection becomes much harder when the networks involve a large number of attributes and become the multi-attributed networks. With the multi-attributed characteristic, most existing approaches are unable to solve this problem effectively and efficiently since it involves the anomalous connected subgraph detection and attributes selection simultaneously. In view of this, this paper proposes a general framework, namely multi-attributed anomalous subgraphs and attributes scanning (MASA), to solve this problem in multi-attributed networks. We formulate and optimize a great number of complicated nonparametric scan statistic functions that are employed to measure the joint anomalousness of the connected subgraphs and the corresponding subset of attributes in multi-attributed networks. More specifically, we first propose to transform each formulated nonparametric scan statistic function into a set of sub-functions with the theoretical analysis. Then using techniques of the tree approximation priors and the dynamic algorithms, an efficient approximation algorithm is presented to solve each transformed sub-function. Finally, with three real-world datasets from different domains, we conduct extensive experimental evaluations to demonstrate the effectiveness and efficiency of the proposed approach.

Computing support-minimal subfunctions during functional decomposition

The growing popularity of look-up table (LUT)-based field programmable gate arrays (FPGA's) has renewed the interest in functional or Roth-Karp decomposition techniques. Functional decomposition is a powerful decomposition method that breaks a Boolean function into a set of subfunctions and a composition function. Little attention has so far been given to the problem of selecting good subfunctions after partitioning the input variables into the disjoint bound and free sets. Therefore, the extracted subfunctions usually depend on all bound variables. In this paper, we present a novel decomposition algorithm that computes subfunctions with a minimal number of inputs. This reduces the number of LUT's and improves the usage of multiple-output SRAM cells. The algorithm iteratively computes subfunctions; in each iteration step it implicitly computes a set of possible subfunctions and finds a subfunction with minimal support. Moreover, our technique finds nondisjoint decompositions, and thus unifies disjoint and nondisjoint decomposition. The algorithm is very fast and yields substantial reductions of the number of LUT's and SRAM cells.

A framework for design of multivalued logic functions and its application using CMOS ternary switches

Two important problems in implementing multi-valued logic (MVL) as compared to binary logic (BL) are the lack of an efficient logic minimization technique and larger chip area and power consumption for realizing an MVL function. In this paper, a new theory for the implementation of MVL is proposed in an attempt to address these problems. In the proposed theory, an MVL function is decomposed into a set of subfunctions that can be efficiently realized using switches that are multivalued-in-nature. Each switch consists of a group of more elementary switches, called subswitches. A complete set of algebraic operators and relations are presented to facilitate the construction of the switches from a set of subswitches. The proposed algebra can be used to minimize the number of subswitches required for each switch in a function realization. Application of the proposed theory to implementing a ternary logic (TL) truth table is illustrated which is expected to encourage further investigation into exploring the possibility of using TL as a competitor to BL. The realization of subswitches is done using CMOS transistors that has potential for a VLSI implementation which can have a small chip area and consume low power.

Some Studies on the Problem of Three-level NAND Network Synthesis

ABSTRACT The present paper is concerned with the problem of three-level economic NAND synthesis of general Boolean functions. It is shown that a. given Boolean function is first decomposed into a set of sub-functions, called φ functions. From a study of the properties of φ functions a method is finally suggested for three-level synthesis of Boolean functions with a fewer number of NAND gates. A method of finding the minimal three-level NAND solution for a given irredundant prime implicant cover of any Boolean function is also suggested.

The Multipurpose Bias Device—Part II: The Efficiency of Logical Elements

The efficiency of a logical element can be equated with the set of subfunctions it realizes upon biasing or duplication of inputs. Various classes of elements are considered, and optimum or near-optimum examples are presented. Some related areas of study are suggested.