A framework for design of multivalued logic functions and its application using CMOS ternary switches

Abstract

Two important problems in implementing multi-valued logic (MVL) as compared to binary logic (BL) are the lack of an efficient logic minimization technique and larger chip area and power consumption for realizing an MVL function. In this paper, a new theory for the implementation of MVL is proposed in an attempt to address these problems. In the proposed theory, an MVL function is decomposed into a set of subfunctions that can be efficiently realized using switches that are multivalued-in-nature. Each switch consists of a group of more elementary switches, called subswitches. A complete set of algebraic operators and relations are presented to facilitate the construction of the switches from a set of subswitches. The proposed algebra can be used to minimize the number of subswitches required for each switch in a function realization. Application of the proposed theory to implementing a ternary logic (TL) truth table is illustrated which is expected to encourage further investigation into exploring the possibility of using TL as a competitor to BL. The realization of subswitches is done using CMOS transistors that has potential for a VLSI implementation which can have a small chip area and consume low power.