Series Field Programmable Gate Arrays Research Articles

Design of a Power Efficient Model of PWM Generator for Green Communication using High Performance FPGAs

Aim: This paper will focus on promoting the ideas of green communication Background: Pulse Width Modulation (PWM) generator is used to control the power transfer in any communication model. It is one of the most crucial parts of an electrical circuit. Our main focus in this research work is to develop an energy and power-efficient PWM generator by using Field Programmable Gate Array (FPGA) logic to elevate green communication Objective: Our main focus in this research work is to develop an energy and power-efficient PWM generator by using Field Programmable Gate Array (FPGA) logic to elevate green communication. Methods: In order to make the PWM suitable for GC, we have implemented the design on VIVADO ISE from Xilinx. The power analysis as well as resource utilization are targeted on three different FPGAs. Results: Different IO standards of Stub Series Terminated Logic (SSTL) family are explored at different FPGA’s. Power analysis is deployed on the 7 series FPGAs of 3 different categories i.e., Spartan 7 (channel length = 28 nm), Kintex 7 (channel length = 20 nm) and ultra scale Zynq 7 (channel length = 16 nm). Conclusion: It can be concluded from power analysis that SPARTAN-7 device is the most powerefficient and ZYNQ Ultra scale+utilizes the highest amount of power. However, KINTEX-7 Ultrascale device lies in the middle of both these devices as far as power consumption is concerned. There is a reduction of 43.07% TP consumption for SPARTAN-7 device with SSTL135 IO when equated with ZYNQ Ultra scale+ with SSTL18_I IO. Also, it can be observed from sections 5.1, 5.2 and 5.3 that there is more contribution of DP in TP consumption than SP. Hence the device utilizes additional power when it is in active state than static state. Since PWM generator is an integral part of data and wireless communication, it should require less power for proficient transmission and wellorganized green computing and communication.

An Optimized Hardware Implementation of a Non-Adjacent Form Algorithm Using Radix-4 Multiplier for Binary Edwards Curves

Binary Edwards Curves (BEC) play a pivotal role in modern cryptographic processes and applications, offering a combination of robust security as well as computational efficiency. For robust security, this article harnesses the inherent strengths of BEC for the cryptographic point multiplication process by utilizing the Non-Adjacent Form (NAF) algorithm. For computational efficiency, a hardware architecture for the NAF algorithm is proposed. Central to this architecture is an Arithmetic Logic Unit (ALU) designed for streamlined execution of essential operations, including addition, squaring, and multiplication. One notable innovation in our ALU design is the integration of multiplexers, which maximize ALU efficiency with minimal additional hardware requirements. Complementing the optimized ALU, the proposed architecture incorporates a radix-4 multiplier, renowned for its efficiency in both multiplication and reduction. It eliminates resource-intensive divisions, resulting in a substantial boost to overall computational speed. The architecture is implemented on Xilinx Virtex series Field-Programmable Gate Arrays (FPGAs). It achieves throughput-to-area ratios of 14.819 (Virtex-4), 25.5 (Virtex-5), 34.58 (Virtex-6), and 37.07 (Virtex-7). These outcomes underscore the efficacy of our optimizations, emphasizing an equilibrium between computational performance and area utilization.

The HSPC — a high speed PCIe readout card for the HFRS-TPC

A new High-Speed PCI Express (PCIe) readout Card (HSPC) has been designed to transmit and aggregate data from the Time Projection Chamber (TPC) that will be assembled on High energy FRagment Separator (HFRS) beamlines at the High Intensity heavy-ion Accelerator Facility (HIAF) currently being built in Huizhou City, China. The HSPC features a high-performance controller utilizing the Xilinx Kintex Ultrascale Series Field Programmable Gate Array (FPGA), two Quad Small Form-factor Pluggable Plus (QSFP+) connectors, and a PCIe Gen3×8 interface with theoretical bandwidth of 64 Gbps. Experimental testing shows that there are no errors on the 8-fiber optics when operating at 9.6 Gbps per link, and the bit error rate (BER) is less than 1.0 × 10-15. In addition, the total read bandwidth of PCIe Gen3×8 reaches 7085.4 MB/s. Consequently, the HSPC can meet HFRS requirements.

A compact and efficient AES-32GF for encryption in small IoT devices

The phenomenal growth of resource constrained devices in IoT set ups has motivated the researchers to develop solutions for securing information flow. In this paper, we present a compact and efficient field programmable gate array (FPGA) implementation of AES with 32-bit data-path named, AES-32GF. The implementation is carried out on different Xilinx FPGAs. In FPGAs, utilization of slices and look up tables (LUTs) reflect on the compactness of the design. Numerical results show that lesser resources are required with smaller data path in comparison with the original standard. With the help of data path compression and Galois field implementation of the s-box resource consumption is minimized. S-box is the most resource consuming component in the AES structure. In our implementation, Artix-7 series FPGA for the same. It results in significant resource savings. In comparison to unrolled AES-128 architecture, it achieves 87 % resource savings. With 595 slices and 2.004 Gbps throughput, AES-32GF cipher achieves an efficiency of 3.37 Mbps/slice. It outperforms other designs in terms of efficiency.•A compact and efficient FPGA implementation of AES with 32-bit data-path has been proposed.•The proposed design utilizes data path compression and Galois field implementation of the s-box to minimize resource consumption.•With 595 slices and 2.004 Gbps throughput, AES-32GF cipher achieves an efficiency of 3.37 Mbps/slice.

FPGA‐based control strategy of five‐phase induction motor drives

Here, a novel control technique for Five-Phase Induction Motor (FPIM) drives using a field-programmable gate array (FPGA) controller is proposed. Open-loop control is analysed in terms of the performance and measurement of various power quality factors, such as voltage harmonics, current harmonics, total harmonic distortion, crest factor, unbalanced, short and long-term flickering, K-factor, real power, reactive power, apparent power, and power factor. This study experimentally demonstrated a closed-loop system with both PID and DTC controls for the FPIM. Diminished torque pulsation is obtained by efficiently utilizing the voltage vectors from the total states of 25 = 32. A novel EG voltage vector sequence was proposed for DTC techniques and compared with small, medium, and large voltage vector sequences. Proposed innovative control programming techniques in spartan-6 XC6SLX25 series FPGA for switching the five-phase two-level inverter to reduce the total harmonics distortion by less than 2%.

Design and implementation of two-dimensional digital finite impulse response filter using very high speed integrated circuit hardware description language

<span>The main purpose of this paper is to design a two-dimensional digital finite impulse response (FIR) filter using data broadcast and non-broadcast structure. The implementation of two-dimensional digital FIR filter is done using very high speed integrated circuit hardware description language (VHDL). Rectangular window method is used for calculating 2D digital FIR filter coefficients for data broadcast and non-broadcast structure. The coefficients of the one-dimensional digital FIR filter are obtained using the MATLAB filter design and analysis (FDA) tool for two different cut-off frequencies and are multiplied to get the necessary coefficient for the two-dimensional FIR filter to be designed; the simulation is done on Artix-7 series field programmable gate array (FPGA), target device (xc7a35t-cpg236) using Vivadov.2015.2. The proposed design reduces the area utilization and the power consumption when compared with the existing literature. The experimental result shows that the power consumption is improved by 97% and there is an improvement of 24% in area utilization for the two-dimensional with and without data broadcast one dimensional FIR filter structures.</span>

Low overhead optimal parity codes

The error detecting and correcting codes are used in critical applications like in intensive care units, defense applications, and require highly reliable data. This brief focuses on codes to detect and correct adjacent errors within a single clock cycle by using modulo-2 addition of data bits for parity generation, syndrome calculation, error location identification and correction by improving code rate and minimizing bit overhead. The optimal parity codes devised can correct odd number of adjacent errors upto (N/2)-1 data bits when compared with the existing codes with less delay. Four optimal codes are proposed using existing decimal matrix codes properties. The proposed codes prove better in terms of area, delay, power, bit overhead, code rate, code efficiency, and with good reliability. The components are developed in veriloghardware description language and verified for zynq 7000 series field programmable gate array in xilinx integrated synthesis environment 14.5 Tool. Among the codes devised, optimal code-4 proves to be a better code with 65.3% code rate and 53.12% bit overhead. Also when compared with other codes, it uses 33.3% less area and 1.89% less power delay product for encoder and 32.2% less area and 0.36% power delay product for decoder respectively.

Neuromorphic Time-Multiplexed Reservoir Computing With On-the-Fly Weight Generation for Edge Devices.

The human brain has evolved to perform complex and computationally expensive cognitive tasks, such as audio-visual perception and object detection, with ease. For instance, the brain can recognize speech in different dialects and perform other cognitive tasks, such as attention, memory, and motor control, with just 20 W of power consumption. Taking inspiration from neural systems, we propose a low-power neuromorphic hardware architecture to perform classification on temporal data at the edge. The proposed architecture uses a neuromorphic cochlea model for feature extraction and reservoir computing (RC) framework as a classifier. In the proposed hardware architecture, the RC framework is modified for on-the-fly generation of reservoir connectivity, along with binary feedforward and reservoir weights. Also, a large reservoir is split into multiple small reservoirs for efficient use of hardware resources. These modifications reduce the computational and memory resources required, thereby resulting in a lower power budget. The proposed classifier is validated for speech and human activity recognition (HAR) tasks. We have prototyped our hardware architecture using Intel's cyclone-10 low-power series field-programmable gate array (FPGA), consuming only 4790 logic elements (LEs) and 34.9-kB memory, making it a perfect candidate for edge computing applications. Moreover, we have implemented a complete system for speech recognition with the feature extraction block (cochlea model) and the proposed classifier, utilizing 15 532 LEs and 38.4-kB memory. By using the proposed idea of multiple small reservoirs along with on-the-fly generation of reservoir binary weights, our architecture can reduce the power consumption and memory requirement by order of magnitude compared to existing FPGA models for speech recognition tasks with similar complexity.

A reconfigurable integrated level shifted carrier based PWM method for modular multilevel converters

This article presents a reconfigurable integrated level shifted carrier‐based pulse width modulation (ILSC‐PWM) method for modular multilevel converters (MMCs). The principles of basic level shifted carrier‐based PWM (LSC‐PWM) methods such as phase disposition PWM (PD‐PWM), phase opposition disposition PWM (POD‐PWM) and alternate phase opposition disposition PWM (APOD‐PWM) methods are combined to develop the concept of reconfigurable ILSC‐PWM method. The main objectives of the proposed reconfigurable ILSC‐PWM method is to develop the pulse width modulated output voltage with both half‐wave and quarter‐wave symmetries and to reduce the total harmonic distortion (THD). A simplified mathematical approach is developed to formulate reconfigurable single ILSC wave for MMC with N number of submodules (SMs) per arm. The functionality and performance of the reconfigurable ILSC‐PWM method are carried out on three‐phase five‐level MMC in MATLAB/Simulink. A hardware prototype of single‐phase five‐level MMC is designed for experimental validation. The proposed ILSC‐PWM method is implemented on an Altera/Cyclone I series (EP1C12Q240C8N) field programmable gate array (FPGA). Computer Simulations and laboratory experimental results are presented. © 2022 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

In-Filter Computing for Designing Ultralight Acoustic Pattern Recognizers

We present a novel in-filter computing framework that can be used for designing ultra-light acoustic classifiers for use in smart internet-of-things (IoTs). Unlike a conventional acoustic pattern recognizer, where the feature extraction and classification are designed independently, the proposed architecture integrates the convolution and nonlinear filtering operations directly into the kernels of a Support Vector Machine (SVM). The result of this integration is a template-based SVM whose memory and computational footprint (training and inference) is light enough to be implemented on an FPGA-based IoT platform. While the proposed in-filter computing framework is general enough, in this paper, we demonstrate this concept using a Cascade of Asymmetric Resonator with Inner Hair Cells (CAR-IHC) based acoustic feature extraction algorithm. The complete system has been optimized using time-multiplexing and parallel-pipeline techniques for a Xilinx Spartan 7 series Field Programmable Gate Array (FPGA). We show that the system can achieve robust classification performance on benchmark sound recognition tasks using only ~ 1.5k Look-Up Tables (LUTs) and ~ 2.8k Flip-Flops (FFs), a significant improvement over other approaches.

Representing Weighted Binary Codes using FPGA

Nowadays machines are playing major role in any development. We need a language or code to communicate with machine. These language or codes must be machine readable and acceptable. Several weighted binary codes have been developed to simplify the communication process between man and machine. In this paper, some of weighted binary codes such as 5421, 5211, 2421 and 4221 are represented by using Artix7 series Field Programmable Gate Array (FPGA) board. Very High Speed Hardware Description Language (VHDL) language is used to design a system which represents these weighted binary codes on FPGA board. Two FPGA switches are used to select weighted binary codes. Four bits inputs of each weighted binary codes are passed using four FPGA switches. Four bits output of each weighted binary codes are represented by using seven segment display and four LEDs of FPGA Board. Xilinx Vivado2015.2 tool is used to do the synthesis and simulation of the proposed system.

FPGA Implementation of 5G NR Primary and Secondary Synchronization

The 5G communication systems are widely established for high-speed data processing to meet users demands. The 5G New Radio (NR) communications comprise a network of ultra-low latency, high processing speeds, high throughput and rapid synchronization with a time frame of 10 ms. Synchronization between User Equipment (UE) and 5G base station known as gNB is a fundamental procedure in a cellular system and it is performed by a synchronization signal. In 5G NR system, Primary Synchronization Signal (PSS) and Secondary Synchronization Signal (SSS) are used to detect the best serving base station with the help of a cell search procedure. The paper aims to determine the Physical Cell Identity (PCI) by using primary synchronization and secondary synchronization blocks. The PSS and SSS detection for finding PCI is implemented on Zynq-7000 series Field Programmable Gate Arrays (FPGA) board. FPGA are reconfigurable devices and easy to design complex circuits at high frequencies. The proposed architecture employs Primary Synchronization Signal (PSS) and Secondary Synchronization Signal (SSS) detection aims with high speed and low power consumption. The synchronization blocks have been designed and the synthesized design block is implemented on the Zynq-7000 series Zed board with a maximum operating clock frequency of 1 GHz.

A high precision phase measurement system implemented in FPGA with phase interpolator.

High precision timing distribution is crucial to many large scale cosmology and particle physics experiments. Besides the space and energy information, the accurate timing provides an extra dimension for physics event reconstruction. In the timing distribution system, accurate clock phase measurement is an indispensable tool to monitor the phase drift and to achieve accurate phase adjustment. This paper introduces a novel phase measurement method implemented in the Xilinx Field Programmable Gate Array (FPGA). It uses the dedicated phase interpolator in the multi-gigabit transceiver. A design based on this method is implemented within the Kintex Ultrascale series FPGA. The preliminary test result shows that a sub-picosecond level precision is achieved. With this system, the nonlinearity of the phase adjustment in the Xilinx transceiver is measured.

Improvements in space radiation-tolerant FPGA implementation of land surface temperature-split window algorithm

The trend in satellite remote sensing assignments has continuously been concerning using hardware devices with more flexibility, smaller size, and higher computational power. Therefore, field programmable gate arrays (FPGA) technology is often used by the developers of the scientific community and equipment for carrying out different satellite remote sensing algorithms. This article explains hardware implementation of land surface temperature split window (LST-SW) algorithm based on the FPGA. To get a high-speed process and real-time application, VHSIC hardware description language (VHDL) was employed to design the LST-SW algorithm. The paper presents the benefits of the used Virtex-4QV of radiation tolerant series FPGA. The experimental results revealed that the suggested implementation of the algorithm using Virtex4QV achieved higher throughput of 435.392 Mbps, and faster processing time with value of 2.95 ms. Furthermore, a comparison between the proposed implementation and existing work demonstrated that the proposed implementation has better performance in terms of area utilization; 1.17% reduction in number of Slice used and 1.06% reduction in of LUTs. Moreover, the significant advantage of area utilization would be the none use of block RAMs comparing to existing work using three blocks RAMs. Finally, comparison results show improvements using the proposed implementation with rates of 2.28% higher frequency, 3.66 x higher throughput, and 1.19% faster processing time.

A hybrid level shifted carrier‐based PWM technique for modular multilevel converters

This paper presents a hybrid level shifted carrier-based pulse width modulation (HLSC-PWM) technique for modular multilevel converters (MMCs). The concept of the proposed HLSC-PWM method is developed by combining the principles of phase disposition PWM (PD-PWM), phase opposition disposition PWM (POD-PWM), and alternate phase opposition disposition PWM (APOD-PWM) methods. The main aim of the proposed HLSC-PWM method is to generate an output voltage with half-wave and quarter-wave symmetries. The generated symmetrical PWM output voltage based on the proposed HLSC-PWM method provides less total harmonic distortion (THD) and enhances the DC-Link voltage utilization (DCLVU). A generalized mathematical model is formulated to develop a single HLSC for MMC with an N number of submodules (SMs) per arm. Theoretical analysis of DCLVU for the proposed method is described. The functionality and performance of the HLSC-PWM method are carried out on a three-phase five-level MMC in MATLAB/Simulink. A hardware prototype of a single-phase five-level MMC is designed for experimental validation. The proposed HLSC-PWM method is implemented on an Altera/Cyclone I series (EP1C12Q240C8N) field-programmable gate array (FPGA), simulation and experimental results are presented.

A Voltage Balancing Scheme for Modular Multilevel Converter Based on Charge Variation in Each Cycle

This article presents a voltage balancing scheme for a modular multilevel converter (MMC) based on capacitor charge variation in each fundamental cycle. An in-depth theoretical analysis of stored charge variation for the concept is described. A new hybrid pulsewidth modulation (PWM) sequence is proposed based on a rotation strategy to achieve capacitor voltage balancing without sensing the capacitor voltages or arm currents. The rotation strategy provides the freedom of finding the best possible sequence to achieve capacitor voltage balancing. This reduces hardware, software burden and overall cost of the design implementation. The functionality and performance of the balancing strategy with new hybrid PWM sequence are carried out over wide range of modulation index (M) for three-phase five-level MMC in MATLAB/Simulink. A hardware prototype of single-phase five-level MMC is designed for experimental validation. The proposed hybrid PWM sequence is implemented on an Altera/Cyclone I series (EP1C12Q240C8N) field-programmable gate array using alternate phase opposition disposition PWM method. Simulation and experimental results are presented.

An Improved Throughput for Non-Binary Low-Density-Parity-Check Decoder

Low-Density-Parity-Check (LDPC) based error control decoders find wide range of application in both storage and communication systems, because of the merits they possess which include high appropriateness towards parallelization and excellent performance in error correction. Field-Programmable Gate Array (FPGA) has provided a robust platform in terms of parallelism, resource allocation and excellent performing speed for implementing non-binary LDPC decoder architectures. This paper proposes, a high throughput LDPC decoder through the implementation of fully parallel architecture and a reduction in the maximum iteration limit, needed for complete error correction. A Galois field of eight was utilized alongside a non-uniform quantization scheme, resulting in fewer bits per Log Likelihood Ratio (LLR) for the implementation. Verilog Hardware Description Language (HDL) was used in the description of the non-binary error control decoder. The propose decoder attained a throughput of 10Gbps at 400-MHz clock frequency when synthesized on a ZYNQ 7000 Series FPGA.

Multibillion packet lookup for next generation networks

Fast Internet Protocol Version 4 (IPv4) lookup is one of the key challenges that have always been faced with growing internet speed. Next generation networks promise hundreds of gigabit communication bandwidths. To support such high data rates, core networking devices require very fast IPv4 lookup for incoming packets to sustain their functionality. Researchers from academia and industry have contributed widely towards this problem, presenting numerous techniques and algorithms to improve lookup times. In this paper, a bit vector-based IP lookup engine is presented that implements parallel units to achieve 4.3 Billion Packets Per Second (BPPS) lookup speeds for 5 fields. Implementations are done using dual port Distributed RAM (DRAM) on state-of-the-art Xilinx Virtex 7 series Field Programmable Gate Arrays (FPGA). Post place and route results for different configurations showed that the proposed design consumes much less memory, facilitating multiple engines on a single chip whilst maintaining a very low overall power profile.

High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis

The Deflate compression algorithm provides one of the most widely used solutions for lossless data compression. Field-programmable gate arrays (FPGAs) are commonly used to implement hardware accelerators that speed up computation-intensive applications. In this article, FPGA-based accelerators for Deflate compression and decompression are described. These accelerators were specified in C++ and synthesized using Vivado High-Level Synthesis (HLS) for a Xilinx Virtex UltraScale+ series FPGA and a system clock frequency of 250 MHz. The proposed compressor processes data at a fixed input throughput of 4.0 GB/s and achieves a geometric mean compression ratio of 1.92 on the Calgary corpus benchmark files using static Huffman encoding. While not the first compressor synthesized using high-level synthesis, our design achieves a 25% greater throughput and an 11% greater compression ratio than the only other published design that uses Vivado HLS. The proposed decompressor design achieves average input throughputs of 196.61 MB/s and 97.40 MB/s, for statically and dynamically encoded Calgary corpus files, respectively. This is the first published decompressor design that is synthesized using high-level synthesis and provides performance that is comparable to that of the best published designs, having static throughputs 11% higher and dynamic throughputs only 10% lower than the expertly-optimized design sold by Xilinx.

Low Cost Hardware Architecture of Fast Lifting Wavelet Transform for Image Compression

In this work, the researchers have given a low-cost, multiplier-less design with latest DWT (2D lifting technology) for high-speed dual-Z scans. A single dimension parallele row, column processors and five transposing registers are the suggested architecture. Furthermore, a 4N timeline buffer is used to process 2D DWT images with NxN resolution. Flipping architecture is intended to decrease the critical path, replacing multipliers with shifting and adding logic. To reduce transposition and latency buffers, dual Z scanning technology is introduced. The proposed architecture is better for similar performance requirements than the existing hardware architectures. Verilog is defined as the suggested Design Register Transfer Logic (RTL) and is synthesized with Xilinx ISE 14.5. When synthesized with a better hardware efficiency for Xilinx Spartan 6 series field programmable gate array, the suggested architecture works at a frequency of 140.47 MHz.