FPGA Implementation of 5G NR Primary and Secondary Synchronization

Abstract

The 5G communication systems are widely established for high-speed data processing to meet users demands. The 5G New Radio (NR) communications comprise a network of ultra-low latency, high processing speeds, high throughput and rapid synchronization with a time frame of 10 ms. Synchronization between User Equipment (UE) and 5G base station known as gNB is a fundamental procedure in a cellular system and it is performed by a synchronization signal. In 5G NR system, Primary Synchronization Signal (PSS) and Secondary Synchronization Signal (SSS) are used to detect the best serving base station with the help of a cell search procedure. The paper aims to determine the Physical Cell Identity (PCI) by using primary synchronization and secondary synchronization blocks. The PSS and SSS detection for finding PCI is implemented on Zynq-7000 series Field Programmable Gate Arrays (FPGA) board. FPGA are reconfigurable devices and easy to design complex circuits at high frequencies. The proposed architecture employs Primary Synchronization Signal (PSS) and Secondary Synchronization Signal (SSS) detection aims with high speed and low power consumption. The synchronization blocks have been designed and the synthesized design block is implemented on the Zynq-7000 series Zed board with a maximum operating clock frequency of 1 GHz.