Architecture and FPGA implementation of LTE PSS and SSS synchronizer

Abstract

This paper presents an architecture of the LTE signal receiver system to acquire the physical cell identity (PCI). The PCI plays an important role to determine other reference signals, which are further used in channel estimation, cell selection/reselection, and handover procedures. The information required to determine the PCI is carried by two LTE synchronization signals: Primary Synchronization Signal (PSS) and Secondary Synchronization Signal (SSS). This paper describes an architecture of PSS and SSS Synchronizer Blocks for LTE-FDD 4G Baseband Receiver System. The synthesis results using Altera Quartus software show that the proposed design of each block consumes 5895 logic gates with the maximum frequency of 114.97 MHz for PSS Synchronizer block and 1332 logic gates with the maximum frequency of 375.09 MHz for SSS Synchronizer block. Both designs have been successfully implemented and verified on Altera DE4 FPGA board.