Series Connected SiC MOSFETs Research Articles

A Control Strategy for Reducing Voltage Ripples in Series-Connected SiC MOSFETs Using Active Clamping Modules in High Power VSCs

A Control Strategy for Reducing Voltage Ripples in Series-Connected SiC MOSFETs Using Active Clamping Modules in High Power VSCs

A Passive Voltage-Balancing Method for Series-Connected SiC MOSFETs in Pulse Generator Based on Snubber Circuit

A Passive Voltage-Balancing Method for Series-Connected SiC MOSFETs in Pulse Generator Based on Snubber Circuit

Quasi-two-level method as an universal approach for voltage balancing of series-connected SiC MOSFETs

Quasi-two-level method as an universal approach for voltage balancing of series-connected SiC MOSFETs

Phase Shift Angle Segmentation Modulation for Soft-Switching Medium-Voltage DAB Converter With Series-Connected SiC MOSFETs

Medium voltage (MV) dual active bridge (DAB) converter with series-connected SiC MOSFETs (S-SiC) is a promising solution for high power density isolated DC/DC converter. To improve the voltage sharing and reliability of S-SiC, relatively large snubber capacitors are connected in parallel with S-SiC. But this narrows the zero voltage switching-on (ZVS-on) range of S-SiC, and even reduces the efficiency and reliability of the entire converter. Adding non-optimized internal phase shift angle to the low-voltage (LV) side switching unit will result in excessive circulating power and still lead to low efficiency. In this paper, the phase-shift angle segmentation modulation (PSSM) scheme featuring soft-switching performance is proposed for a MV DAB converter with S-SiC. The proposed modulation scheme is based on a detailed derivation of the ZVS-on range and operation modes. Then, the changes in operation characteristics and the advantages brought by the proposed modulation scheme are analyzed in terms of transmission power, state transition process, switching current and device losses. Moreover, the introduced modes and ZVS-on characteristics are verified on the 4kV/1kV 200kW experimental prototype. As a result, the converter’s loss can be decreased by up to 75% under light load, validating the efficiency advantage of the proposed modulation scheme.

A Hybrid Current- and Voltage-Source Driver for Active Driving of Series-Connected SiC MOSFETs

A Hybrid Current- and Voltage-Source Driver for Active Driving of Series-Connected SiC MOSFETs

A Novel Boost Marx Pulse Generator Based on Single-Driver Series-Connected SiC MOSFETs

This paper presents a new type of all solid state boost Marx pulse generator (BMPG). On the basis of the classic pulse forming Marx circuit, without changing the voltage level of each voltage module, a new switch is added for the isolated inductor energy storage and recovery, so as to realize the output of high-voltage nanosecond pulses. At the same time, in order to improve the voltage level of the semiconductor switch and break the limitation of the voltage of the single-stage pulse forming circuit, a series-connected SiC MOSFETs with a single external driver is designed. The series switch has a simple structure with few components and is extremely easy to use in a modular high voltage pulse generator. Its theoretical feasibility is verified by mathematical model and circuit simulation, and the 10-stage prototype is built in this paper. Under the condition of input DC voltage of 500 V, it can output 18 kV high voltage pulses of 200 ns-1200 ns, and the gain multiple has reached 36 times.

Analysis and Design for Medium Voltage Dual Active Bridge Converter Based on Series-Connected SiC MOSFETs

Analysis and Design for Medium Voltage Dual Active Bridge Converter Based on Series-Connected SiC MOSFETs

Voltage Balancing of Series-Connected SiC mosfets With Adaptive-Impedance Self-Powered Gate Drivers

Voltage Balancing of Series-Connected SiC mosfets With Adaptive-Impedance Self-Powered Gate Drivers

Magnetic-Coupled and Low-Cost Gate Driver for Series-Connected SiC MOSFETs

Magnetic-Coupled and Low-Cost Gate Driver for Series-Connected SiC MOSFETs

Analysis and Flexible DV/DT Control of an Active Clamping Topology for Series-Connected SiC MOSFETs

Series-connection of SiC MOSFETs is an attractive solution to build cost effective and high efficiency medium voltage converters, however, the unequal voltage sharing among the power devices and the induced high d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> /d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> problems should be considered carefully. In this paper, an active clamping topology and corresponding d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> /d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> control method for series-connected SiC MOSFETs are proposed. With the proposed topology, the drain-source voltage of each SiC MOSFET can be clamped by discrete clamping capacitor, resulting in high robust switching. Besides, the clamping capacitor voltages can be auto-balanced during the topology operation, so the peak voltages of the series-connected SiC MOSFETs can be easily balanced. By simply adjusting the gate drive delay time, the proposed topology could reduce the equivalent d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> /d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> of the device string with very small increase in power loss, so the high d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> /d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> induced switching noise can be suppressed greatly. Finally, a 4.8kV/10A half-bridge prototype is established with 6 SiC MOSFETs connected in series within per bridge arm, experimental results are provided to show the effectiveness and advancement of the proposed method.

A Hybrid Dynamic Voltage Sharing Scheme for Series-connected SiC MOSFETs with Single Gate Drive

At present, the voltage level of a commercial SiC MOSFET can hardly meet the requirements of high-voltage field. For the sake of achieving the application of MOSFETs in high-voltage fields, the method of series-connected MOSFETs has become a practical and effective solution. However, multiple series-connected SiC MOSFETs face the problem of voltage unbalance, especially dynamic voltage unbalance. Generally, the problem of dynamic unbalance could be solved using load side voltage sharing schemes or the methods of gate side. This paper uses a hybrid dynamic voltage sharing scheme for the single-driven series-connected SiC MOSFETs. That is to say, based on a sequential lagging single gate drive topology, combining active clamping circuits with RCD snubber circuits are introduced to solve the problem of dynamic voltage unbalancing of the whole module in this paper. Compared to the circuit without any dynamic voltage sharing scheme, the dynamic voltage imbalance degree of the circuit with a hybrid dynamic voltage sharing scheme is decreased to 3.75% during the switching-on and switching-off periods. The equalization effect would be verified through the simulation under clamped inductive load in LTspice.

Design of a Gate-Driving Cell for Enabling Extended SiC MOSFET Voltage Blocking

A series connection of SiC MOSFETs for kV blocking capability can enable more design flexibility in modular multi-level converters as well as other topologies. In this paper, a novel gate driver circuit capable of driving series-connected SiC MOSFETs for high voltage applications is proposed. The primary advantage of the proposed design is that a single gate driver was used to switch all the series devices. The circuit used switching capacitors to sequentially charge and discharge device gate capacitances during switching and enable a negative turn-off voltage to avoid device coupling from Miller-capacitive feedback effects. With the proposed gate driver design and appropriate component values selection, avalanche breakdown due to voltage divergence during switching transients could be avoided with only a minor imbalance in the top device. Simulations and experimental measurements showed that the zero-current turn-off transition of all switches was achieved, and this approved the validity of the design.

Hybrid Voltage Balancing Approach for Series-Connected SiC MOSFETs for DC–AC Medium-Voltage Power Conversion Applications

Using series-connected SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s to enable high-speed switching units is desired to meet the growing demand for high-density medium-voltage power converters. Due to its fast-switching speed, the voltage sharing of series-connected SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s is more sensitive to the surrounding parasitic components and gate-signal mismatch, which results in more challenges for the voltage balancing control. In this article, the gate turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> delay-time control is first used as an example to analyze the limitations of the existing active voltage balancing (AVB) control methods: 1) AVB control has a limitation of adjusting the delay time accurately under ac current conditions; and 2) the voltage imbalance of the body diodes cannot be solved by AVB control. To achieve voltage balancing control of series-connected SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s for ac current, this article proposes a new hybrid approach: 1) passive <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> compensation: one small compensation capacitor is applied to balance the measured nonuniform distribution of parasitic capacitors <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">;</i> and 2) active gate signal turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> time adjustment: a digital closed-loop delay time control is applied to compensate the gate signal mismatch of <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s. To verify the proposed balancing approach, a single-phase pump-back test is conducted to show the improvement of voltage sharing of both <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s and body diodes.

Experimental Investigation of a 10 kV-70A Switch with Six SiC-MOSFETs in a Series-Connection Configuration

In this paper, a prototype of 6 series-connected SiC-MOSFETs for double pulses test purpose is presented. This prototype represents many challenges amongst which the measurements of voltage sharing and the EMI issues due to high dv/dt. High voltage tests are performed up to 8 kV at 65A and voltage balancing, losses and switching speeds are evaluated. Switching speed up to 520 V/ns are recorded.

Analytical Model and Design of Voltage Balancing Parameters of Series-Connected SiC MOSFETs Considering Non-Flat Miller Plateau of Gate Voltage

Series connection is an attractive approach to increase the blocking voltage of SiC power MOSFETs. Currently, the voltage balancing design of the series connection of the SiC MOSFETs highly relies on offline calibration and is challenging in the complex field operation. In this paper, a quantitative model to assess the voltage balancing performance is proposed to achieve a clear mathematical interpretation of the dynamic response of the voltage imbalance control loop. To begin with, an analytical model of the drain-source voltage rising time during the turn-off transient concerning the non-constant Miller plateau is proposed. Based on the turn-off model of the single device, the voltage imbalance sensitivity (VIS) is proposed to describe the influence of the parameters on the gate driving signals on the voltage imbalance. The VIS parameter can be easily achieved from the behavior of single devices, abandoning the complex variables in series connection. Further, for the typical case, active time delay voltage balancing methods are selected to demonstrate the application of the VIS analysis method. Based on VIS, the accurate close-loop design is proposed for controlling the delayed time among the devices. The proposed analysis and method are verified in simulation and experiment. The paper offers a generalized approach to assess the performance and the design of the series connection of the SiC MOSFETs, which can be further applied in many other methods for parameter design and engineering applications.

A Comprehensive Short-Circuit Protection Scheme for Series-Connected SiC MOSFETs

Series connection of devices is an effective way to achieve higher blocking voltage. SiC MOSFETs exhibit narrow short-circuit withstand time and generally much lower short-circuit robustness than silicon IGBTs. This puts a critical concern on their utilization, further stressing the importance of reliable protection. A complete short-circuit protection should be implemented to improve the reliability. In this article, a systematic short-circuit analysis methodology is proposed. Following this methodology, all the possible fault scenarios can be derived. Besides the traditional short-circuit scenarios, some unique short-circuit faults, such as a single device short- or open- circuit, have been found in series-connected SiC MOSFETs. These unique faults may not cause overcurrent, which means the traditional overcurrent-based protection is not applicable. This article proposes a method combining drain-source voltage logic signal and gate signal to comprehensively detect both classic short-circuit scenarios and unique fault scenarios. Another different point in series-connected devices is that the soft turn-off should be synchronized for each serial device to prevent excessive voltage unbalancing. The proposed short-circuit protection scheme is evaluated under each short-circuit scenario. The experimental results demonstrate that the proposed protection scheme can successfully protect the serial devices from further destruction within 500 ns for all short-circuit scenarios.

Stability Analysis and Improvement for SSCB With Single-Gate Controlled Series-Connected SiC MOSFETs

Silicon carbide-based solid-state circuit breaker (SSCB) exhibits superior performance in dealing with the interruption of dc short-circuit current compared with the mechanical switch. The blocking voltage of commercially available SiC devices still cannot meet the voltage requirements. Series-connected SiC mosfets providing higher blocking voltage based SSCB with the single-gate driver has been proposed previously. However, the sustained oscillation phenomenon, unacceptable false gate-trigger, and severely unbalanced voltage distribution have been observed after the energy-absorbing stage in the circuit. These phenomena are mainly caused by the capacitor coupling mechanism among the two series-connected devices due to specific circuit configuration. This article elaborates on the mechanism of the oscillation by establishing the small-signal models. Based on the stability criterion analysis, an effective damping method is proposed to improve the stability of the SSCB. Simulation and experimental tests have been conducted to verify the effectiveness of the proposed damping method.

A Universal Block of Series-Connected SiC MOSFETs Using Current-Source Gate Driver

SiC MOSFET has superior switching performance over Si IGBT in terms of power loss and temperature characteristics. In order to significantly improve the efficiency and power density of medium-voltage drive and high-power converters, this article proposes a current-source gate driver (CS-GD) for series-connected SiC MOSFETs, forming a universal block of series-connected SiC devices with the higher voltage rating. The proposed CS-GD has better gate voltage synchronization performance because of its constant gate current and novel gate driver structure. By implementing synchronized gate voltages, the snubber circuit is designed only for power loop difference and gate displacement current difference, and the snubber can be minimized or even be eliminated. The proposed block has been verified by LTSPICE simulations and multipulse test experiments under 200-kHz, 2-kV, 0~60-A condition using three 1.2-kV/60-A C2M0040120D SiC MOSFETs connected in series.

A Modified RC Snubber With Coupled Inductor for Active Voltage Balancing of Series-Connected SiC MOSFETs

Series connection of SiC power MOSFET is an attractive approach to expand the blocking voltage of SiC devices, whereas the dynamic voltage balancing among the series-connected devices is the most critical challenge of the technique. In this article, a simple, fast, and cost-effective dynamic voltage balancing circuit of the series-connected SiC MOSFETs is proposed to suppress the voltage imbalance among the devices. The proposed circuit is composed of a resistor-capacitor (RC) snubber with a coupled inductor to effectively sense the voltage imbalance and add a compensated signal to the gate driving voltage. In the article, the operation principle of the proposed method is described in detail and the parameter selection of the circuit is given. Then the optimized layout of the circuit in a typical half-bridge SiC power module is proposed to reduce the stray parameters introduced by the coupled inductor effectively. The proposed method is verified by experiments under different conditions. Compared with a purely RC snubber balancing strategy, the capacitor can be significantly reduced. Since only passive components are required in the feedback loop, the proposed method demonstrates a reliable and straightforward approach to achieve equal voltage sharing of the series-connected devices.

Analysis of Voltage Sharing of Series-Connected SiC MOSFETs and Body-Diodes

In recent years, SiC MOSFETs have gained strong attention in medium-voltage power conversion applications. To increase the blocking voltage level, series-connection of SiC MOSFETs is an attractive solution but may suffer a severe voltage unbalance issue. To gain insights into the voltage unbalance issue, this article presents a detailed study of the impact of parasitic capacitors on the voltage sharing of series-connected SiC MOSFETs and body-diodes. The parasitic capacitors are categorized into two groups for analysis: 1) parasitic capacitors from gate terminal; 2) parasitic capacitors from drain/source terminals. The study reveals that gate parasitic capacitors affect gate miller-plateau voltage and ultimately the dv/dt during the turn-off. The voltage sharing will be worse under higher turn-off current or larger gate resistor. The drain/source parasitic capacitors will introduce additional capacitance across device drain-source terminals which results in an unbalanced voltage sharing. The position of switching unit and the heatsink connection schemes will affect the distribution of drain/source parasitic capacitors to cause different voltage sharing results. The drain/source parasitic capacitors will also cause voltage unbalance of series-connected body-diodes under different conditions. To verify the analysis, the voltage sharing between two series-connected 10 kV SiC MOSFETs is tested under different parasitic capacitors conditions.