Serial Link Receiver Research Articles

A new flip-flop based on discrete-time parametric amplifier

This paper introduces a low power flip-flop based on the discrete-time parametric amplifier, with improved rise (fall) time, setup-time, hold-time, and area. Post-layout simulation result of the proposed flip-flop in a 180 nm CMOS technology with 3.33 GHz frequency illustrates about 21% of the power consumed by CML flip-flop and about 30% improvement in the clock-to-q delay. Also, the simulation shows improved rise (fall) time, lower data-to-q delay compared to dynamic CML and Footless flip-flop, lower area than Charge Steering flip-flops without the need for additional return-to-zero to non-return-to-zero conversion circuitry. When using this flip-flop as a slicer in a decision feedback equalizer (DFE) circuit of a serial link receiver of 1 m Nelco backplane channel, the post-layout simulation results show that the DFE circuit based on the parametric flip-flop has about 50% improvement of power consumption in comparison with the conventional CML DFE circuit in identical conditions.

A Fully Digital Semirotational Frequency Detection Algorithm for Bang–Bang CDRs

This brief presents a new frequency acquisition method using a semirotational frequency detection (SRFD) algorithm for referenceless clock and data recovery (CDR) in a serial-link receiver. The proposed SRFD algorithm classifies the bang–bang phase detector (BBPD) outputs to estimate the current phase state and detects the frequency mismatch between the input data and the sampling clock. The voltage-controlled oscillator (VCO)-track path in a digital loop filter (DLF) enables online calibration of a drifted frequency of the VCO caused by temperature or voltage variation after a frequency acquisition. The proposed algorithm can be implemented as a digitally synthesized circuit, lowering design efforts for referenceless CDRs. A 10-Gb/s transceiver IC with the proposed algorithm, fabricated in a 65-nm CMOS process, demonstrates successful recovery of the input phase without any reference clock.

Modeling of ADC-Based Serial Link Receivers With Embedded and Digital Equalization

Serial link receivers with high-speed analog-to-digital converters (ADCs) can utilize powerful digital-domain equalizers and support multilevel modulation schemes. This paper presents a hybrid statistical modeling framework for ADC-based serial link receivers. The framework builds upon the existing statistical modeling techniques for mixed-signal receivers and adds the support of ADC quantization noise, radix errors [integral nonlinearity and differential nonlinearity (INL/DNL)], and time-interleaving mismatches. A rapid purely statistical simulation mode is utilized to model systems with small front-end nonlinearity and ADC INL/DNL. To include ADC INL/DNL, a hybrid approach is presented with an initial short transient simulation. The presented modeling framework is used to explore the effectiveness of embedding an analog feed-forward equalizer (FFE) in the ADC of a 10-Gb/s receiver. Measurement results of a 10-Gb/s ADC-based receiver prototype with a three-tap embedded FFE in the ADC and a digital four-tap FFE and three-tap decision feedback equalizer are presented to validate the presented framework.

Comparator hysteresis compensation for decision feedback equalisers

High-speed comparators are extensively used in serial link receiver designs. Some comparator architectures can show significant hysteresis that degrade the sensitivity of the receiver, increasing the bit error rate. In this Letter, a comparator hysteresis compensation strategy that re-uses the first tap of a decision feedback equaliser to shift the comparator input voltage, increasing the decision margin is proposed. An updated equaliser coefficient adaptation scheme is also introduced. The proposed technique can be used for binary and multi-level modulations.

A study of analog decision feedback equalization for ADC-Based serial link receivers

High-speed serial link receivers based on analog-to-digital converters (ADCs) provide better programmability with different channel characteristics and the possibility of employing powerful signal equalization techniques in the digital domain. However, complexity and power consumption are still major issues in adopting such receivers in high-speed applications when compared to traditional binary or mixed-signal approaches. Embedded decision feedback equalization (DFE) before ADC quantization can relax the design requirements of both the ADC and post-ADC digital processing. This paper studies the impact of embedded analog DFE on voltage margin improvement of an ADC-based receiver through worst-case analysis. An analytical expression for the link bit-error-rate (BER) with analog DFE is derived and validated through simulations. An empirical study is conducted that evaluates the achievable BER of embedded analog DFE as a function of the channel inter-symbol interference (ISI) and ADC resolution. A channel-dependent parameter is introduced and employed to quantify the BER improvement achieved by embedding analog DFE in a receiver. A prototype receiver with embedded DFE is designed and laid out in a 130 nm CMOS process and achieves 4.64-bits peak ENOB and 4.08 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. The BER performance of the receiver over high-loss FR4 channels at 1.6 Gb/s is evaluated and used to validate the simulation results.

Continuous‐time linear equalizer with automatic boosting gain adaptation and input offset cancellation

SummaryA continuous‐time linear equalizer (CTLE) for high‐speed serial link is presented whose adaptive boosting gain is obtained with the data and edge values sampled by clock and data recovery circuit. The input offset of the serial link receiver is estimated by the data and edge values as well and cancelled by the CTLE. The adaptation of the CTLE boosting gain is immune to the phase error of the clock and data recovery sampling clock, and the cancellation of the input offset is independent of the boosting gain adaptation. The performance of the proposed adaptive CTLE has been evaluated by applying it to a 5‐Gb/s serial link receiver implemented in a 65‐nm CMOS technology.

A 5-bit 1.8 GS/s ADC-based receiver with two-tap low-overhead embedded DFE in 130-nm CMOS

Along with CMOS technology scaling, ADC-based serial link receivers have drawn growing interest in backplane communications but power dissipation of the ADC and complex digital equalizer in such digital receivers can be a limiting factor in high-speed applications. Implementing analog embedded equalization within the front-end ADC structure can potentially relax the ADC resolution requirement and reduces the complexity of the DSP which results in a more energy-efficient receiver. In this paper, the equivalence between the speculative comparisons of a loop-unrolling DFE and an ADC with non-uniform quantization levels is utilized to propose a novel ADC-based DFE receiver structure. The equivalency partially compensates for the power overhead imposed by loop-unrolling DFE. The 5-bit prototype receiver with two-tap embedded DFE is designed, laid out and simulated in a 130-nm CMOS process with 1.8 Gbps data rate. With embedded DFE disabled, the receiver achieves 4.57-bits ENOB and 1.77 pJ/conv.-step FOM. With 1.8-Gbps signaling across a 48-in FR4 channel, the two-tap DFE enabled receiver opens the completely closed eye and allows for a 0.26 UI timing margin at a BER of 10−9. The total active area is 0.21 mm2 and the ADC consumes 76 mW from a 1.2-V supply.

Analysis and Design of Single Reference Reduced Summer Loading-Based Switched Capacitor DFE

Decision feedback equalizers (DFE) are an integral part of modern serial link receivers. Attenuation in wireline communication channels causes pulse spreading. Hence, multi-tap post-cursor cancellation is necessary for reliable recovery of data at the receiver. However, the addition of multiple taps causes loading on the analog summing node which degrades the bandwidth of operation. This paper explores the design parameters of a switched capacitor-based DFE for multi-tap post-cursor cancellation with reduced summer loading. The architecture is validated by post-layout simulations done in UMC65SP technology. A PRBS-7 generator is used, and test cases are simulated upto 4.0 Gbps for two different channel attenuations around 20 dB.

A Low-Power Three-Tap DFE with Switched Resistor Slicer and CTLE in 0.18μm CMOS Technology

In this paper, a switched resistor slicer is proposed to reduce the power consumption of a decision feedback equalizer (DFE). In the proposed structure, summer circuit that consumes most of the power in a DFE has been eliminated and proper resistors are added as the load of a slicer based on a flip-flop output bit stream. Incorporating the proposed DFE circuit with continuous time linear equalizer (CTLE) at the serial link receiver over a 1[Formula: see text]m NELCO (the NELCO[Formula: see text] N4000-13 series is an enhanced epoxy resin system engineered to provide both outstanding thermal and high signal speed/low signal loss properties) channel can compensate 24[Formula: see text]dB loss at the Nyquist frequency of 2[Formula: see text]GHz. CTLE is adjusted to compensate 6[Formula: see text]dB of channel loss which remains after utilizing a DFE with three taps. The proposed structure has been designed in 0.18[Formula: see text][Formula: see text]m CMOS technology while consuming 13.5[Formula: see text]mW from 1.8[Formula: see text]V supply at 4[Formula: see text]Gb/s with a bit error rate less than 10[Formula: see text]. The proposed equalizer power consumption is reduced by 43% compared to the conventional circuit.

A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS

While high-speed analog-to-digital converter (ADC) front-ends in serial link receivers enable flexible and powerful digital signal processing-based (DSP-based) equalization, the robustness and power consumption of these ADCs can limit overall receiver energy efficiency. This paper presents a 25 GS/s 6b 8-way time-interleaved multi-bit search ADC that employs a soft-decision selection algorithm to relax track-and-hold (T/H) settling requirements and improve ADC metastability tolerance. T/H bandwidth is also improved with a new shared-input double-tail three-latch structure. Fabricated in general purpose 65 nm CMOS, the ADC occupies 0.24 mm2 total area. A signal-to-noise and distortion ratio (SNDR) of 29.6 dB is achieved at Nyquist while consuming 88 mW from a 1 V supply, translating into a figure-of-merit of 143 fJ/conversion step. A measured $^{-10}$ metastability error rate demonstrates the effectiveness of the soft-decision selection algorithm.

CMOS ADC-based receivers for high-speed electrical and optical links

CMOS ADC-based serial link receivers enable powerful digital equalization and symbol detection techniques for high data rate operation over electrical and optical wireline channels. Common ADC architectures and equalization techniques that allow 10 Gb/s and higher operation are surveyed in this article. As time-interleaving is most often employed to achieve these high sampling rates, the associated errors and calibration techniques are presented. The impact of ADC quantization noise on receiver performance and how this can be improved via embedded partial analog equalization are detailed. A description of a 65 nm CMOS hybrid ADC-based receiver architecture that employs a 3-tap analog FFE embedded inside a 6-bit asynchronous successive approximation register (SAR) ADC and a per-symbol dynamically enabled digital equalizer operating at 10 Gb/s concludes the discussion.

A Study of BER-Optimal ADC-Based Receiver for Serial Links

Analog-to-digital converter (ADC)-based multi-Gb/s serial link receivers have gained increasing attention in the backplane community due to the desire for higher I/O throughput, ease of design portability, and flexibility. However, the power dissipation in such receivers is dominated by the ADC. ADCs in serial links employ signal-to-noise-and-distortion ratio (SNDR) and effective-number-of-bit (ENOB) as performance metrics as these are the standard for generic ADC design. This paper studies the use of information-based metrics such as bit-error-rate (BER) to design a BER-optimal ADC (BOA) for serial links. Channel parameters such as the $m$ -clustering value and the threshold non-uniformity metric $h_{t}$ are introduced and employed to quantify the BER improvement achieved by a BOA over a conventional uniform ADC (CUA) in a receiver. Analytical expressions for BER improvement are derived and validated through simulations. A prototype BOA is designed, fabricated and tested in a 1.2 V, 90 nm LP CMOS process to verify the results of this study. BOA's variable-threshold and variable-resolution configurations are implemented via an 8-bit single-core, multiple-output passive digital-to-analog converter (DAC), which incurs an additional power overhead of $ 0.1% (approximately 50 $\mu\text{W}$ ). Measurement results show examples in which the BER achieved by the 3-bit BOA receiver is lower by a factor of $10^{9}$ and $10^{10}$ , as compared to the 4-bit and 3-bit CUA receivers, respectively, at a data rate of 4-Gb/s and a transmitted signal amplitude of 180 mVppd.

Low‐power charge‐steering phase interpolator

The demand for low-power equalisation at high data rates in serial-link receivers has prioritised the issue of power consumption. This high demand has also involved the phase-locked loop (PLL) and clock and data recovery (CDR) circuits. This propelled efforts to further optimise the PLLs and CDRs building blocks and to pursue low-power solutions. A charge-based phase interpolator (PI) is presented. It employs charge-steering circuits in order to reduce the power typically consumed by its current-based counterpart. Implemented in 65-nm CMOS technology, a 6-bit charge-based PI consumes 180 μW at 1–V supply and 5-GHz clock.

A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization

While analog-to-digital converter (ADC)-based serial link receivers enable powerful digital equalization for high data rate operation, the ADC and digital equalization power consumption is a key concern in applications that support operation over a wide range of channels with varying amounts of intersymbol interference (ISI). This paper presents a hybrid ADC-based receiver architecture which employs a 3-tap analog feed-forward equalizer (FFE) embedded inside a 6 bit asynchronous successive approximation register (SAR) ADC and a per-symbol dynamically enabled digital equalizer, resulting in both reduced equalizer complexity and power consumption. Fabricated in general purpose (GP) 65 nm CMOS, the hybrid ADC-based receiver occupies $0. 81\; \text{mm}^{2}$ area. 10 Gb/s operation is verified for FR4 channels with up to 36.4 dB attenuation, with the proposed dynamic enabling of the digital 4-tap FFE and 3-tap decision feedback equalizer (DFE) on a per-symbol basis resulting in nearly 30 mW savings and an overall receiver power less than 90 mW.

10 Gbit/s serial link receiver with speculative decision feedback equaliser using mixed‐signal adaption in 65 nm CMOS technology

A 10 Gbit/s serial link receiver with an offset-calibrated continuous-time linear equaliser, an adaptive one-tap half-rate speculative decision feedback equaliser (DFE) and a phase-interpolator-based clock and data recovery is presented. Adaption of the DFE is achieved by using a novel mixed-signal implementation of the sign-sign least mean square algorithm to save the cost of hardware and power. Fabricated in 65 nm CMOS technology, the receiver can totally compensate 24.85 dB channel loss at a bit error rate of 10−12. The active chip area is 0.08 mm2 and the total power consumption is 57 mW from a 1.2 V supply.

An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator

Cameras and image sensors have recently been installed in many portable devices. An image processor and a transceiver are also adopted in multimedia system-on-a-chip to handle the data from the image sensor. A wide input range and flexible data bandwidth are needed for the serial link receiver to deal with various sensor specifications. This paper presents an 11.2-Gb/s low-voltage differential signaling (LVDS) receiver for various portable devices that employ a LVDS system for data transmission between an image sensor and a processor. The designed LVDS receiver has 16 data channels and four clock channels. All the channels are selectively turned on or off, depending on the application. The proposed comparator used for the input driver of the receiver has a rail-to-rail input range and 60 mV of minimum input swing level. The clock dividing ratio and the data de-serializing factor of the proposed receiver are also programmable to deal with various color depths of image sensors. The designed LVDS receiver is fabricated in a 0.13-μm CMOS process, occupying 4-4 mm, with a 7.24-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core. Power consumption is 77.38 mW, when every channel is turned on.

A Multichannel Serial Link Receiver With Dual-Loop Clock-and-Data Recovery and Channel Equalization

This paper presents a four channel receiver for high-speed signal conditioning. Each channel consists of a continuous time linear equalizer (CTLE) and a dual loop CDR with phase-interpolator. All channels share a single PLL that generates and distributes quadrature clock phases to each CDR for data recovery. Clock amplitude, phase INL and phase DNL are derived for IQ phase error and predict phase-dependent jitter contributions to the recovered clock. The multilane receiver was designed in 130-nm CMOS technology. The die occupies an area of 1930 μm by 1250 μm and consumes 67.9 mW per channel. It achieves a maximum data rate of 7 Gbps per channel for 0 and ±200 ppm clock frequency deviation.

A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS

ADC-BASED serial link receivers are emerging in order to scale data rates over high attenuation channels. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-efficient receiver. This paper presents a 6-b 1.6-GS/s ADC with a novel embedded DFE structure. A redundant cycle technique is proposed for a time-interleaved SAR ADC, which relaxes the DFE feedback critical path delay with low power/area overhead. The 6-b prototype ADC with embedded one-tap DFE is fabricated in an LP 90-nm CMOS process and achieves 4.75-bits peak ENOB and 0.46 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. Enabling the embedded DFE while operating at 1.6 Gb/s over a 46-in FR4 channel with 14-dB loss at Nyquist bandwidth opens a previously closed eye and allows for a 0.2 UI timing margin at a BER=10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> . Total ADC power including front-end T/Hs and reference buffers is 20.1 mW, and the core time-interleaved ADC occupies 0.24 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area.

Design and Simulation of High Speed, Low Powered ADC for Serial link Receiver

This paper presents design & Simulation of High Speed, Low Powered ADC for Serial link Receiver. This ADC based receiver uses a low gain analog and mixed mode pre-equalizer in conjunction with the non-uniform reference levels for ADC. This combination compensates for both front-end nonideality and the channel response while maintaining low ADC resolution and hence enables low power consumption. This receiver is based on a low power design of Analog to Digital converter, thus lowering the power consumption of overall system. Tanner tool 13.0 is used for the simulation of the proposed design. From the simulation results it has been observed that the modules used in the proposed ADC lowers the power consumption. Keyworks-Serial link receiver, digital equalizer, Sequence detector, Analog-to-Digital Converter

채널 등화기를 내장한 2.0GS/s 5비트 전류 모드 ADC 기반 수신기

본 논문에서는 고속 직렬 링크에 사용할 수 있는 5비트 2.0GS/s 2-way time interleaved 파이프라인 ADC 기반의 수신기를 소개한다. 샘플링 주파수를 높이기 위해, ADC 각 단은 트랙킹과 증폭이 동시에 수행되는 전류 모드 구조를 사용하였다. 또한 ADC 각단에 1-tap FIR 등화기를 탑재하여 별도의 디지털 후처리 없이 채널의 ISI를 감소시켰다. 제안한 수신기는 110nm 공정을 사용하여 설계하였다. 메모리를 제외한 수신기는 <TEX>$0.58{\times}0.42mm^2$</TEX>의 크기를 갖고, 동작전압 1.2V에서 91mW의 전력을 소모한다. 시뮬레이션 결과 2.0GS/s 샘플링 주파수에서 20MHz의 입력 주파수와 Nyquist 주파수인 1.0GHz 입력신호에 대하여 동일하게 26.0dB의 SNDR과 4.0비트의 ENOB특성을 확보하였다. In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is <TEX>$0.58{\times}0.42mm^2$</TEX>. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.