A study of analog decision feedback equalization for ADC-Based serial link receivers

Abstract

High-speed serial link receivers based on analog-to-digital converters (ADCs) provide better programmability with different channel characteristics and the possibility of employing powerful signal equalization techniques in the digital domain. However, complexity and power consumption are still major issues in adopting such receivers in high-speed applications when compared to traditional binary or mixed-signal approaches. Embedded decision feedback equalization (DFE) before ADC quantization can relax the design requirements of both the ADC and post-ADC digital processing. This paper studies the impact of embedded analog DFE on voltage margin improvement of an ADC-based receiver through worst-case analysis. An analytical expression for the link bit-error-rate (BER) with analog DFE is derived and validated through simulations. An empirical study is conducted that evaluates the achievable BER of embedded analog DFE as a function of the channel inter-symbol interference (ISI) and ADC resolution. A channel-dependent parameter is introduced and employed to quantify the BER improvement achieved by embedding analog DFE in a receiver. A prototype receiver with embedded DFE is designed and laid out in a 130 nm CMOS process and achieves 4.64-bits peak ENOB and 4.08 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. The BER performance of the receiver over high-loss FR4 channels at 1.6 Gb/s is evaluated and used to validate the simulation results.