Serial Input Data Research Articles

Ultra-optimized demultiplexer unit design in quantum-dot cellular automata nanotechnology

Integrated circuit designers face challenges in using complementary metal oxide semiconductor (CMOS) technology as it has a large leakage current and scalability challenge in ultra-nanoscale regime. Quantum-dot Cellular Automata (QCA) is a nanotechnology that can replace CMOS for designing ultra-deep submicron circuits and overcoming CMOS limitations. In this research paper, a novel area-efficient 1:2 demultiplexer is proposed using QCA technology. A demultiplexer is an important combinational circuit used in communication systems and computer memories. It receives serial input data and routes data in parallel to multiple outputs. QCA Designer and QCA Pro-tools are used for layout, simulation, and analysis of power dissipation. 11 QCA cells are utilized in the construction of the proposed 1:2 demultiplexer. The cell area and layout cost of the proposed demultiplexer have improved to 42.11 % and 55.56 % of the current best design, respectively. An essential factor to consider when developing integrated circuits is power dissipation. The proposed design dissipates less power. The energy dissipation of the proposed design has improved to 57.67 % at the kink energy level of 1.5 of the current best design.

A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT

In this brief, we present a novel pipelined architecture for real-valued fast Fourier transform (RFFT), which is dedicated to processing serial input data. An optimized algorithm is proposed for stage division in RFFT to achieve an area-efficient RFFT computing structure with full hardware utilization. A single path butterfly and a real rotator are merged into one processing element (PE) in each stage, except the last stage, to reduce hardware resource utilization. In addition, a novel shift-adder is designed for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> -point RFFT with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$ </tex-math></inline-formula> -bit signals, and a new data management method based on the PEs is proposed, which saves resources with a more regular flow graph.

A Low Cost 4 bit 16 Giga-sample-per-second Analog-to-digital Converter for Radio Astronomy

In this study, a 4 bit, 16 giga samples per second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was designed, manufactured, and characterized for digitizing signals from radio telescopes. For this purpose, an Adsantec ANST7123-KMA flash ADC chip was used. Because this design of chip is not followed the serial ADC JESD204 standard completely, we used a novel channel bonding scheme developed in our previous project for the high-speed serial data input alignment. The PCBA was equipped with a field-programmable gate array (FPGA) mezzanine card (FMC) connector. FMC allowed us to use the FPGA evaluation board by Xilinx as the testing platform. The PCBA enables data acquisition with a wide bandwidth and simplifies the intermediate frequency section. In the current version, the PCBA and the chip exhibit an analog bandwidth of 16 GHz, which facilitates a second Nyquist sampling. The following minimum to maximum performance parameters were obtained from the first and second Nyquist zones: a spurious-free dynamic range of 18–33 dB and an effective number of bits of 2.1–3.7 bits. The board will be ported to the Collaboration for Astronomy Signal Processing and Electronics Research environment, which is open for use by non-profit scientific teams, including the Event Horizon Telescope.

Implementation of a Depth from Light Field Algorithm on FPGA

A light field is a four-dimensional function that grabs the intensity of light rays traversing an empty space at each point. The light field can be captured using devices designed specifically for this purpose and it allows one to extract depth information about the scene. Most light-field algorithms require a huge amount of processing power. Fortunately, in recent years, parallel hardware has evolved and enables such volumes of data to be processed. Field programmable gate arrays are one such option. In this paper, we propose two hardware designs that share a common construction block to compute a disparity map from light-field data. The first design employs serial data input into the hardware, while the second employs view parallel input. These designs focus on performing calculations during data read-in and producing results only a few clock cycles after read-in. Several experiments were conducted. First, the influence of using fixed-point arithmetic on accuracy was tested using synthetic light-field data. Also tests on actual light field data were performed. The performance was compared to that of a CPU, as well as an embedded processor. Our designs showed similar performance to the former and outperformed the latter. For further comparison, we also discuss the performance difference between our designs and other designs described in the literature.

Circuitry of multiplexer-on-chip system within the micro-LED array manufacturing CMOS substrate

In this paper, this research is after the process CMOS driver substrate. It is the use of A Benzocyclobutene polymer thin films planarization coating material in elements of the LED array manufacturing process. This CMOS driver circuit is a mode architecture that uses serial input data and parallel output data. It is the use of shift registers and latch circuit cell to form the overall system chip. The current density of the microcrystalline LED elements of each size is the same condition. The current density of a single 16 μm microcrystalline LED pixel driven by a 2.85 V drive circuit board is about 2.69 μA.

SISTEM KONTROL PADA ROBOT PEMINDAH BARANG TIPE CARTESIAN CORDINAT MENGGUNAKAN ARDUINO UNO R3

Robots are an option to help human jobs address issues of precision, security and flexibility. The robot&lt;br /&gt;arm becomes one of the robot types that can help human work. The robot arm controller research is&lt;br /&gt;to control the stepper motor's motion according to the command. Desai this cartesian coordinate&lt;br /&gt;robot is 2 axis that is X and Y axis. Control of this robot arm using Visual Basic 6.0 programming for&lt;br /&gt;controlled robot from PC to arduino Uno R3. Motor driver used is IC A4988, stepper motor movement&lt;br /&gt;got input from PC with software visual basic 6.0. to move the stepper motor. Data sent from PC to&lt;br /&gt;Arduino Uno R3 is a command from Visial Basic 6.0 with serial communication. The microcomputer&lt;br /&gt;reads the serial data input and sends a step value data to the stepper motor driver to move the robot&lt;br /&gt;arm. The end result of the robot arm controller research that has been achieved is the robot arm can&lt;br /&gt;be controlled with the command to enter the distance that will be run by stepper motor as the&lt;br /&gt;method of pemograman which is controlled through serial communication with Visual Basic 6.0. The&lt;br /&gt;test results show an average error 22.26531 for the left and 52.61111 for the right direction on X axis&lt;br /&gt;while for Y axis -5,36957 for the downward direction and 0.117647 for the upper direction

SPECIFIC FEATURES OF CORRELATION RECEPTION OF ULTRASHORT PULSES

A method is proposed for obtaining a sequence of ultra-short signals. A correlative method is reviewed for reception of such sequences. Curves of dependence of error probability in serial data input from signal-to-noise ratio in correlation processing have been obtained.

PEMANFAATAN MOTOR SERVO SEBAGAI PENGGERAK CCTV UNTUK MELIHAT ALAT-ALAT MONITOR DAN KONDISI PASIEN DI RUANG ICU

Ahmad Hilal, Saiful Manan, in paper use servo motor as a CCTV driver to see monitoring equipment and conditions of patients in the icu room explain thatservo motor is a motor with a closed feedback system in which the position of the motor will be communicated back to the control circuit in the servo motor, servo motor is able to work both directions (clockwise and belawanan clockwise) in which the direction and angle of the rotor movement can controlled only by providing PWM signal duty cycle settings on the control pin. In the servo motor function of this type is only capable of moving in either direction (CW and CCW) with respective deflection angle reaches 90 ° so that the total deflection angle of the center - right -kiri adalah180 °. Part of the servo motors consist of a potentiometer which functions as a regulator of the servo movement of a large pulse is given, the internal gear serves as a torque amplifier dc servo motors, dc motors as the driving part that converts electrical energy into motion, as well as a control circuit servo motor driver function to process the data input pulses into motion. Servo motors used to drive the CCTV, in order to see the health of the patient monitoring devices as instructed. The servo motor voltage of 5 volts dc power supply from PC. Servo motor movements influenced the input pulse, to round to the right then it takes the pulse of more than 1,5ms, for the leftist movement takes the pulse of less than 1,5ms and at the center position or silence takes input pulse of 1.5 ms with a delay of 20 ms. Servo motors work processes in order to move that the serial data input from the PC, the serial data into the ATMEGA 8 for processing, so that the serial data is converted into binary data through IC74595 as servo motor driver, to output one of IC74595, the servo motor can move, because inflows along with pulses to the servo motor control circuit. Keywords: DC servo motors, Power Supply, IC74595, ATMEGA 8

LOW COMPLEXITY DIGIT SERIAL FIR FILTER BY MULTIPLE CONSTANT MULTIPLICATION ALGORITHMS

Serial input data is multiplied with constant pair to produce constant multiplication called Multiple Constant Multiplications (MCM). In order to reduce number of shifting, an addition/subtraction operation, Graph Based (GB) algorithm is taken as a proposed algorithm to construct multiplier for transposed form of digit serial FIR (Finite Impulse Response) filter design 4-tap digit serial FIR filter with digit size d=2,4,8. To analyze low complexity Digit based recoding algorithm and CSE (Common Subexpression Elimination) algorithm simulation compared with GB algorithm based on the performance of area utilization and delay report in Xilinx ise design suite12.1software. Finally this FIR filter is implemented in FPGA spartan3 hardware for real time implementation.

A 3.4-Gbps clock and data recovery circuit with a forwarded clock in a 0.13-μm CMOS technology

A clock and data recovery (CDR) circuit has been developed for a clock-forwarded 3.4-Gbps serial link. The loss of the signal channel is compensated by a linear equaliser whose output is applied to eight samplers which provides edge- and data-samples of the serial data input. Based on the edge- and data-samples, the phase of a voltage-controlled oscillator (VCO) running at one-fourth of the data rate is adjusted to get the optimum eight-phase sampling clocks. Implemented in a 0.13-μm standard CMOS process, the CDR circuit shows the bit-error rate (BER) less than 10−15.

An Area and Energy Efficient Inner-Product Processor for Serial-Link Bus Architecture

A unique word-serial inner-product processor architecture is proposed to capitalize on the high-speed serial-link bus. To eliminate the input buffers and deserializers, partial products are generated immediately from the serial input data and accumulated by an array of small binary counters operating in parallel to form a reduced partial product matrix directly. The height of the resultant partial product matrix is reduced logarithmically, and hence the carry-save-adder tree needed to complete the inner-product computation is smaller and faster. The small binary counters act as active on-chip buffers to mitigate the workload of the partial product accumulator. Their ability to accumulate partial product bits faster than combinatorial full adder leads to a simple two-stage architecture of high throughput and low latency. The architecture consumes 46% less silicon area, 24% less energy per inner-product computation and 70% less total interconnect length than its merged arithmetic counterpart in 65 nm CMOS process. In addition, the architecture requires only 4 metal layers out of available 7 layers for signal and power routing. By emulating the on-chip serial-link bus architecture on both designs, it is demonstrated that the proposed design is most suited for high-speed on-chip serial-link bus architecture.

Digit-Serial Pipeline Sorter Architecture

This paper presents the VLSI architecture design of pipeline sorter which is suitable for the fast sorting of the continuous serial input data stream. By decomposing the Batcher's merge-sort process into a network of compare-and-swap (C&S) operations, two different styles of pipeline architectures based on the feedback and feed-forward data shuffling modules can be first achieved. However, both architectures suffer the low hardware utilization due to the discrepancy of input sample rate and internal processing rate. Therefore, this paper further proposes a novel digit-serial pipeline sorter architecture by dividing the data into two sub-words. In addition, the most-significant half-word data are processed first in order to reduce the internal register overhead incurred in the C&S unit. Our experimental results show that about 50% saving of gate counts can be achieved by the digit-serial approach.

A Single-Data-Bit Blind Oversampling Data-Recovery Circuit With an Add-Drop FIFO for USB2.0 High-Speed Interface

A compact blind oversampling data-recovery circuit was implemented by using a coarse data-recovery block and an add-drop first-in first out, and it was successfully applied to the universal serial bus (USB)2.0 high-speed packet data transmission. The proposed circuit recovered the serial input data by selecting the sampled data among the 5X oversampled data of a single data bit. It reduced the number of transistors by more than half and the lock time to zero, compared to the conventional blind oversampling data-recovery circuit using the de-multiplexing scheme for multibit-data. The proposed circuit was implemented with a 0.18-m CMOS process. It worked at the data rates ranging from 180 to 720 Mbps. The bit-error rate was measured to be less than with the PRBS data transmitted though a 5-m USB cable. The chip area and the measured power consumption for 480-Mbps operation were 0.185 and 8.2 mW, respectively.

Most-significant-bit-first serial/parallel multipliers

Three serial/parallel multipliers are introduced, which both receive the serial input data and produce the serial product in a most-significant-bit-first (MSB-first) fashion, Advantages of using MSB-first multiplication over conventional least-significant-bit-first multiplication include: efficient calculation of MSB-first data from analogue/digital conversion; efficient interfacing with MSB-first algorithms such as square root and division; and simple truncation of the product. The approach does not utilise any special number system, but multiplier architectures both for unsigned and two's complement number representation (both for the direct and the Baugh-Wooley algorithms) are provided.

A CMOS high-speed data recovery circuit using the matched delay sampling technique

This paper presents a scheme and circuitry for demultiplexing and synchronizing high-speed serial data using the matched delay sampling technique. By simultaneously propagating data and clock signals through two different delay taps, the sampler achieves a very fine sampling resolution which is determined by the difference between the data and clock delays. This high resolution sampling capability of the matched delay sampler can be used in the oversampling data recovery circuit. A data recovery circuit using the matched delay sampling technique has been designed and fabricated in 1.2-/spl mu/m CMOS technology. The chip has been tested at 417 Mb/s [2.4 ns nonreturn to zero (NRZ)] input data and demultiplexes serial input data into four 104 Mb/s (9.6 ns NRZ) output streams with 800 mW power consumption at 4 V power supply. While recovering data, the sampling clock running at 1/4 of the data frequency is phase-tracking with the input data based on information extracted from a digital phase control circuit.

Flexible VLSI architecture of motion estimator for video image compression

A linear array architecture for a full-search block matching algorithm is proposed. It is suitable for low bit-rate video applications with a single chip realization. It uses a parallel algorithm based on the idea of partial result accumulation. Combining a serial data input with registers for a line of search window pixels and operating on them in parallel, the partial results of the candidate block distortions are obtained for all horizontal search positions, which are successively accumulated into a cyclic storage buffer. Based on this scheme, a flexible architecture can be designed for motion vector estimation of different search ranges and block sizes.

VLSI architecture for block-matching motion estimation algorithm

The block-matching motion estimation is the most popular method for motion-compensated coding of image sequence. A VLSI architecture for implementing a full-search block-matching algorithm is presented. Based on a systolic array processor and shift register arrays with programmable length, the proposed architecture has the following advantages: it allows serial data input to save the pin counts but performs parallel processing; it is flexible in adaptation to the dimensional change of the search area via simple control; it can operate in real time for videoconference applications; and it is simple and modular in design, and thus is suitable for VLSI implementation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A planar IrO multichannel stimulating electrode for use in neural prostheses

This paper describes a multisite stimulating probe capable of the precise delivery of sophisticated charge waveforms to neural structures on a chronic basis. The fabrication process for passive probes requires only four masks and is very high yield. Activated iridium oxide stimulating sites are shown to be compatible with the delivery of over 3 mC/cm 2/phase in biphasic charge-balanced operation. In order to minimize the number of external probe leads, on-chip circuitry has been defined to allow per-channel current control at the 8-bit level using serial input data and a total of five external leads.

New microprocessor based approach to binary multiplication using recorded multipliers

Multibit overlapped scanning is used to reduce the time to perform binary multiplication. The scanning and recording of the multiplier vector is done using combinational logic. Circuits for both parallel and serial input data are designed. An implementation using multi-microprocessors is proposed and simulated results are discussed. A possible application to digital filtering is suggested.

A multimicroprocessor architecture for real-time computation of a class of DFT algorithms

The design of a multimicroprocessor system intended for a class of real-time processing applications is discussed. The applications considered require the computation of a subset of an N-input Fourier transform under the assumption of a serial data input. The suitability of two different algorithms and the corresponding parallel architectures is analyzed and compared. More specifically, we compare the computation of the FFT algorithms on an SIMD (single instruction multiple data) machine to the implementation of the DFT algorithm on an MISD (multiple instruction single data) machine. Our results indicate that the latter is better suited for the targeted applications. An actual operational MISD computer, implemented with off-the-shelf microprocessors intended for one of the targeted applications, is described.