Serial In Parallel Out Research Articles

Design of Low Power SAR ADC with Novel Regenerative Comparator

This paper introduces two low-power design techniques for a successive approximation register (SAR) analog-to-digital converter (ADC) used in transmitting physiological signals. The first technique is called dual split switching, involving the use of a one-sided charge-scaling digital-to-analog converter (DAC) to minimize switching energy by reducing leakage in a dual transmission gate. The second technique, known as the set and reset phase, determines the amplification and comparison phases of the comparator. This approach reduces the delay time of the comparator through the use of a folded cascode pre-amplifier and a regenerative latch. The design includes a Serial-in-Parallel-Out (SIPO) N-bit register and SAR, implemented using negative edge-triggered D flip-flops (DFFs). To optimize power consumption, the supply voltage of the SAR ADC is set to 500 mV. The concept of a variable threshold is utilized throughout the design to enable operation with this lower supply voltage. The SAR ADC is designed to support a sampling rate of up to 1 Msps (mega-samples per second). The circuit is implemented using standard UMC180nm technology. According to the test results, the power consumption of the SAR ADC is only 29.06 uW, and the achieved sampling rate is 5 Ksps (kilo-samples per second). The maximum differential non-linearity (DNL) is measured to be +0.9/−0.82 least significant bits (LSBs).

Self-Clocked Shift Registers Utilizing 90 nm CMOS: Design, Analysis and Insights

This paper presents an efficient approach to designing and analyzing four bit shift register utilizing self-clocked D flip-flops as integral storage components. The use of internal clock generation within these flip-flops obviates the need for external clock synchronization. These specially designed flip-flops incorporate a reduced number of transistors in comparison to conventional designs, leading to notable enhancements in power efficiency, packaging density, and operational speed. The implementation of self-triggered D flip-flops facilitates the creation of various shift register configurations, including Serial in Serial out (SISO), Serial in Parallel out (SIPO), Parallel in Serial out (PISO), and Parallel in Parallel out (PIPO). These registers not only occupy a smaller die area but also exhibit diminished power consumption and heightened operational speed when contrasted with standard counterparts. The design and simulation procedures are executed using the Microwind tool and a 90 nm CMOS technology.

QCA-Based PIPO and SIPO Shift Registers Using Cost-Optimized and Energy-Efficient D Flip Flop

With the growing use of quantum-dot cellular automata (QCA) nanotechnology, digital circuits designed at the Nanoscale have a number of advantages over CMOS devices, including the lower utilization of power, increased processing speed of the circuit, and higher density. There are several flip flop designs proposed in the literature with their realization in the QCA technology. However, the majority of these designs suffer from large cell counts, large area utilization, and latency, which leads to the high cost of the circuits. To address this, this work performed a literature survey of the D flip flop (DFF) designs and complex sequential circuits that can be designed from it. A new design of D flip flop was proposed in this work and to assess the performance of the proposed QCA design, an in-depth comparison with existing designs was performed. Further, sequential circuits such as parallel-in-parallel-out (PIPO) and serial-in-parallel-out (SIPO) shift registers were designed using the flip flop design that was put forward. A comprehensive evaluation of the energy dissipation of all presented fundamental flip-flop circuits and other sequential circuits was also performed using the QCAPro tool, and their energy dissipation maps were also obtained. The suggested designs showed lower power dissipation and were cost-efficient, making them suitable for designing higher-power circuits.

Adiabatic logic based shift registers for low energy IoT architecture—Design and contemplation

AbstractShift register is one of the important components in any digital circuit. By improving the performance of shift register, one can improvise the whole system performance. Shift registers are the basic memory units and data transfer devices in IoT applications. The efficacy of computing devices depends on the performance of arithmetic circuits, including shift registers. Adiabatic logic has been proposed as anew computing platform to develop power‐efficient IoT devices. This paper presents low power adiabatic shift registers. The design of shift registers uses D flipflop, based on DC‐DB PFAL (direct‐current diode based positive feedback adiabatic logic). Performance parameters of the presented circuits are analyzed for transistor count, power dissipation, latency, and PDP (power delay product). Simulations are run for all the presented circuits at 180nm and 45nm technology nodes. It is found that the proposed parallel in parallel out shift register (PIPO) design outperforms with the improvement in PDP as 53%, 53%, and 57% compared to theserial in serial out (SISO), serial in parallel out (SIPO), and parallel inserial out (PISO) shift registers respectively at 100MHz and 45 nm technology node. Further, the proposed PIPO shift register shows improved performance than the other designs in the literature.

Design and Implementation of Efficient 8-Bit SIPO Shift Register

Area and power are main design constraints in analog and digital circuits. In this paper, a low-power 8-bit shift register is implemented by using true phase single clock (TSPC) D- flip flop which is based on single clock and two clocked transistors. The proposed design successfully solves the long discharge path problem which is bound to occur in conventional type of D-Flip Flop. This paper describes 8 bit serial in parallel out (SIPO) shift register using True Single-Phase Clock(TSPC) technique which reduces an area in terms of transistor count by 85.29%.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

Design of Reversible Shift Register Using Reduced Number of Logic Gates

Background: Over the last few decades, reversible logic system/circuits have received considerable attention in the diversified fields such as nanotechnology, quantum computing, cryptography, optical computing and low power design of VLSI circuits due to their low power dissipation characteristics. Methods: In this paper, we proposed the design of reversible shift register (SR) i.e. serial-in-serial out (SISO), serial-in-parallel out (SIPO), parallel-in-serial out (PISO) and parallel-in-parallel out (PIPO) SR using a reduced number of reversible logic gates and garbage output. Results: As compared to previously reported results, the improvement in our proposed model of SISO, SIPO, PISO and PIPO was found to be 50 – 66.66 %, 42.85 – 66.66 %, 12.5 – 53.33 % and 50 – 66.66 % respectively, in terms of the number of reversible logic gates.

A low power 10 bit SAR ADC with variable threshold technique for biomedical applications

This paper presents two low power design techniques used for successive approximation registers (SAR) analog-to-digital converter (ADC) for transmission of Physiological signal: Dual split switching; set and reset phase. Dual split switching is used in one sided charge scaling digital-to-analog converter (DAC) to edge of the switching energy by reducing the leakage in dual transmission gate. The set and reset phase defines the amplification and comparison phase of the comparator. The delay time of the comparator is profoundly reduced with folded cascoded pre amplifier and a regenerative latch. A Serial In Parallel Out (SIPO) N bit register and SAR are designed with negative edge triggered D Flip-Flop (DFF). For power optimization the supply voltage of SAR ADC is designed with 500 mV. The Variable threshold concept has been utilized in the entire design to operate the SOC with 500 mV supply voltage. The designed SAR ADC is capable of supporting the sampling rate of 1 Msps. The circuit is designed using standard UMC 180 nm technology. The simulation results show that the power consumption of the SAR ADC is 13.99 μW and achieved 68.54 dB SFDR with ENOB value 7.69 bits. The DNL (max) is + 0.9/− 0.82 LSB and INL 1.06/− 1.31 LSB.

Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study

The detection of catastrophic short and open faults in bipolar current mode logic (CML) circuits is studied. The non-intrusive tests considered include functional (logic) tests, an Idd test, and a common-mode test. A 622 Mbps SONET SIPO (Serial-In/Parallel-Out) and a PISO (Parallel-In/Serial-Out) circuit form the basis of this case study.

A Fast Multichannel Analog Storage System

A Multichannel Analog Storage System based on a commercial 32-channel parallel in/serial out (PISO) analog shift register is described. The basic unit is a single width CAMAC module containing 512 analog cells and the associated logic for data storage and subsequent readout. At sampling rates of up to 30 MHz the signals are strobed directly into the PISO. At higher rates signals are strobed into a fast presampling stage and subsequently transferred in block form into an array of PISO's. Sampling rates of 300 MHz have been achieved with the present device and 1000 MHz are possible with improved signal drivers. The system is well suited for simultaneous handling of many signal channels with moderate numbers of samples in each channel. RMS noise over full scale signal has been measured as 1:3000 (≈11 bit). However, nonlinearities in the response and differences in sensitivity of the analog cells require an elaborate calibration system in order to realize 11 bit accuracy for the analog information.