A low power 10 bit SAR ADC with variable threshold technique for biomedical applications

Abstract

This paper presents two low power design techniques used for successive approximation registers (SAR) analog-to-digital converter (ADC) for transmission of Physiological signal: Dual split switching; set and reset phase. Dual split switching is used in one sided charge scaling digital-to-analog converter (DAC) to edge of the switching energy by reducing the leakage in dual transmission gate. The set and reset phase defines the amplification and comparison phase of the comparator. The delay time of the comparator is profoundly reduced with folded cascoded pre amplifier and a regenerative latch. A Serial In Parallel Out (SIPO) N bit register and SAR are designed with negative edge triggered D Flip-Flop (DFF). For power optimization the supply voltage of SAR ADC is designed with 500 mV. The Variable threshold concept has been utilized in the entire design to operate the SOC with 500 mV supply voltage. The designed SAR ADC is capable of supporting the sampling rate of 1 Msps. The circuit is designed using standard UMC 180 nm technology. The simulation results show that the power consumption of the SAR ADC is 13.99 μW and achieved 68.54 dB SFDR with ENOB value 7.69 bits. The DNL (max) is + 0.9/− 0.82 LSB and INL 1.06/− 1.31 LSB.