Separate Memory Research Articles

Highly fluctuating short-term load forecasting based on improved secondary decomposition and optimized VMD

Short Term Load Forecasting (STLF) is a critical task in the power sector, enabling efficient resource allocation and grid management. However, the volatile and complex nature of short-term load series pose significant challenges to forecasting models. Traditional decomposition-prediction models are bottlenecked in that they often lack complexity-based clustering for efficiency and optimization of decomposition for optimal secondary decomposition. In this paper, we summarize the framework of the decomposition-prediction models, and propose the hybrid model to address these limitations. We propose a Sample Entropy-based hierarchical clustering method to cluster components according to complexity and improve the efficiency of secondary decomposition. Additionally, we propose the center frequency method to efficiently optimize the K parameter of VMD, ultimately achieving the optimal decomposition. In summary, firstly, to help minimize the difficulty of prediction, the load series is decomposed twice using Complete Ensemble Empirical Mode Decomposition with Adaptive Noise (CEEMDAN) and Optimized Variational Mode Decomposition (OVMD). Then, two separate Long Short-Term Memory (LSTM) frameworks are built to predict the components obtained from the two decompositions, thus leveraging the advantages of the previous basic framework. Finally, by superimposing the prediction results, we obtain the output of the proposed model. The Belgian power load dataset is divided into four groups by season for comparison experiments. The results reveal that our model outperforms the benchmark models, with the best average coefficient of determination and mean absolute error of 0.996 and 53.69. Additionally, the limitations of sample entropy in secondary decomposition were revealed through our findings. These insights emphasize the promising contribution that our study brings in enhancing the decomposition-prediction model.

Disruption of Anterior Temporal Lobe Reduces Distortions in Memory From Category Knowledge.

Memory retrieval does not provide a perfect recapitulation of past events, but instead an imperfect reconstruction of event-specific details and general knowledge. However, it remains unclear whether this reconstruction relies on mixtures of signals from different memory systems, including one supporting general knowledge. Here, we investigate whether the anterior temporal lobe (ATL) distorts new memories because of prior category knowledge. In this preregistered experiment (n = 36), participants encoded and retrieved image-location associations. Most images' locations were clustered according to their category, but some were in random locations. With this protocol, we previously demonstrated that randomly located images were retrieved closer to their category cluster relative to their encoded locations, suggesting an influence of category knowledge. We combined this procedure with TMS delivered to the left ATL before retrieval. We separately examined event-specific details (error) and category knowledge (bias) to identify distinct signals attributable to different memory systems. We found that TMS to ATL attenuated bias in location memory, but this effect was limited to exploratory analyses of atypical category members of animal categories. The magnitude of error was not impacted, suggesting that a memory's fidelity can be decoupled from its distortion by category knowledge. This raises the intriguing possibility that retrieval is jointly supported by separable memory systems.

Distinct competitive impacts of palatability of taste stimuli on sampling dynamics during a preference test.

Food or taste preference tests are analogous to naturalistic decisions in which the animal selects which stimuli to sample and for how long to sample them. The data acquired in such tests, the relative amounts of the alternative stimuli that are sampled and consumed, indicate the preference for each. While such preferences are typically recorded as a single quantity, an analysis of the ongoing sampling dynamics producing the preference can reveal otherwise hidden aspects of the decision-making process that depend on its underlying neural circuit mechanisms. Here, we perform a dynamic analysis of two factors that give rise to preferences in a two-alternative task, namely the distribution of durations of sampling bouts of each stimulus and the likelihood of returning to the same stimulus or switching to the alternative-that is, the transition probability-following each bout. The results of our analysis support a specific computational model of decision making whereby an exponential distribution of bout durations has a mean that is positively correlated with the palatability of that stimulus but also negatively correlated with the palatability of the alternative. This impact of the alternative stimulus on the distribution of bout durations decays over a timescale of tens of seconds, even though the memory of the alternative stimulus lasts far longer-long enough to impact the transition probabilities upon ending bouts. Together, our findings support a state transition model for bout durations and suggest a separate memory mechanism for stimulus selection. (PsycInfo Database Record (c) 2023 APA, all rights reserved).

Synaptic devices for simulating brain processes in visual-information perception to persisting memory through attention mechanisms

In the human brain, attention plays a crucial role in encoding information into memory. Therefore, focused attention during encoding enhances the likelihood of information being effectively encoded and stored in memory. This phenomenon is creatively replicated in our proposed synaptic devices, which regulate the forgetting curves by manipulating the gate voltage. Thus, the proposed transistor devices separate long-term memory from long-lasting memory. TiO2-based synaptic transistors are used to replicate brain functions, from vision processing to memory retention. The photosensitive nature of TiO2 enables the utilization of both photo- and electric stimuli. The electrical properties of the synaptic devices induced by photostimulation replicate the human-vision process, while those elicited by electric stimulation simulate memory-retention capabilities. By applying a shallow trap with a short lifetime, light stimulation can be utilized to mimic the effects of short-term memory. A deep trap with a long lifetime is employed in electrical memory to replicate the phenomena associated with persisting memory. A simulation of the MNIST recognition of an artificial neural network constructed with the measured synaptic characteristics exhibit an accuracy rate of 92.96%, which indicates that the proposed device can be successfully incorporated into neuromorphic devices.

In-sensor reservoir computing based on optoelectronic synaptic devices

Artificial neural networks built with optoelectronic synaptic devices have been proven to process visual information effectively. However, it takes great latency time and energy consumption, especially facing dynamic visual information, due to the separated optical sensor, memory, and process unit. Reservoir computing (RC) based on optoelectronic synaptic devices provides an in-sensor RC for processing temporal information efficiently. It achieves efficient computation by sensing and processing optical signals directly with optoelectronic synaptic devices. Optoelectronic synaptic devices shine in visual information processing, whose application in visual sensing and processing will provide a viable hardware solution for in-sensor computing. Therefore, the application of optoelectronic synaptic devices in reservoir computing has prompted increasing attention. Herein, for promoting the application of physical reservoir computing (PRC) with optoelectrical synapses in machine vision, synaptic plasticity will be introduced first in this work and then illustrate the basic functions of optoelectronic synapses as well as their application in reservoir computing further, and provide a perspective on PRC with optoelectronic synapses in the final.

A review on device requirements of resistive random access memory (RRAM)-based neuromorphic computing

With the arrival of the era of big data, the conventional von Neumann architecture is now insufficient owing to its high latency and energy consumption that originate from its separated computing and memory units. Neuromorphic computing, which imitates biological neurons and processes data through parallel procedures between artificial neurons, is now regarded as a promising solution to address these restrictions. Therefore, a device with analog switching for weight update is required to implement neuromorphic computing. Resistive random access memory (RRAM) devices are one of the most promising candidates owing to their fast-switching speed and scalability. RRAM is a non-volatile memory device and operates via resistance changes in its insulating layer. Many RRAM devices exhibiting exceptional performance have been reported. However, these devices only excel in one property. Devices that exhibit excellent performance in all aspects have been rarely proposed. In this Research Update, we summarize five requirements for RRAM devices and discuss the enhancement methods for each aspect. Finally, we suggest directions for the advancement of neuromorphic electronics.

A hierarchical model-based method for wafer level virtual metrology under process information deficiency

Online inspection is one of the most critical processes of quality control in semiconductor manufacturing. The physical inspection methods for wafers are time-consuming and unable to achieve wafer level metrology. In order to improve production efficiency and expand inspection coverage, virtual metrology (VM) methods have recently received widespread attention; they utilize process parameters to estimate wafer metrology results. However, due to process drift and other reasons, the process information contained in real-time signal data (RTS data) used for VM modeling in industrial production is insufficient. This work proposed a hierarchical modeling method for machine learning-based virtual wafer metrology, leveraging RTS and post-process quality characteristics. The hierarchical model consists of an multiway principle analysis (MPCA) sub-model for RTS feature extracting and two separate long short-term memory (LSTM) networks for wafer-to-wafer dynamics in RTS and quality characteristics, respectively. A case study on the thickness VM of chemical vapor deposition thin film is conducted, and the proposed method has achieved better results than other methods in comparison.

Boolean Logic Computing Based on Neuromorphic Transistor

AbstractGeneral‐purpose computers usually use logic gate computing units based on complementary metal oxide semiconductors (CMOS). Due to the separate memory and computing units in Von Neumann architecture, data transmission requires great energy and time consumption. Developing novel neuromorphic devices and comprehensively investigating their logical computing mode are crucial to achieve high‐performance and low‐power neuromorphic computation. Here, a systematic summary of Boolean logic computing based on emerging neuromorphic transistors is presented. This summary encompasses logical operation modes, materials, device structures, and working mechanisms. The input mode of Boolean logic operation is classified into electrical input, optical input, and synergistic optical/electrical input. Besides, additional modulation strategies to construct programmable logic functions by electrical, optical, and thermal signals are also summarized. These strategies hold great significance as they enable dynamic reconfiguration of logic operations and provide neuromorphic devices with decision‐making capabilities. Finally, the application prospects and current challenges to Boolean logic computing based on dendritic integration are discussed from the aspects of device integration, synergistic input/modulation modes, auxiliary peripheral circuit, software/hardware system, etc. It is believed that comprehensive investigations on neuromorphic Boolean logic operations are crucial to push forward the development of future neuromorphic computing toward high efficiency and high integration density.

Concurrent Implicit Adaptation to Multiple Opposite Perturbations.

Simultaneous adaptation to opposite visuomotor perturbations is known to be difficult. It has been shown to be possible only in situations where the two tasks are associated with different contexts, being either a different colored background, a different area of workspace, or a different follow-through movement. However, many of these elements evoke explicit mechanisms that could contribute to storing separate (modular) memories. It remains to be shown whether simultaneous adaptation to multiple perturbations is possible when they are introduced in a fully implicit manner. Here, we sought to test this possibility using a visuomotor perturbation small enough to eliminate explicit awareness. Participants (N = 25) performed center-out reaching movements with a joystick to five targets located 72° apart. Depending on the target, visual feedback of cursor position was either veridical (one target) or could be rotated by +5 or -5° (two targets each). After 300 trials of adaptation (60 to each target), results revealed that participants were able to fully compensate for each of the imposed rotations. Moreover, when veridical visual feedback was restored, participants exhibited after-effects that were consistent with the rotations applied at each target. Questionnaires collected immediately after the experiment confirmed that none of the participants were aware of the perturbations. These results speak for the existence of implicit processes that can smoothly handle small and opposite visual perturbations when these are associated with distinct target locations.

Emerging Memtransistors for Neuromorphic System Applications: A Review.

The von Neumann architecture with separate memory and processing presents a serious challenge in terms of device integration, power consumption, and real-time information processing. Inspired by the human brain that has highly parallel computing and adaptive learning capabilities, memtransistors are proposed to be developed in order to meet the requirement of artificial intelligence, which can continuously sense the objects, store and process the complex signal, and demonstrate an "all-in-one" low power array. The channel materials of memtransistors include a range of materials, such as two-dimensional (2D) materials, graphene, black phosphorus (BP), carbon nanotubes (CNT), and indium gallium zinc oxide (IGZO). Ferroelectric materials such as P(VDF-TrFE), chalcogenide (PZT), HfxZr1-xO2(HZO), In2Se3, and the electrolyte ion are used as the gate dielectric to mediate artificial synapses. In this review, emergent technology using memtransistors with different materials, diverse device fabrications to improve the integrated storage, and the calculation performance are demonstrated. The different neuromorphic behaviors and the corresponding mechanisms in various materials including organic materials and semiconductor materials are analyzed. Finally, the current challenges and future perspectives for the development of memtransistors in neuromorphic system applications are presented.

High-fat-sugar diet is associated with impaired hippocampus-dependent memory in humans

Overconsumption of high-fat and high-sugar (HFS) diet may affect the hippocampus, and consequently, memory functions. Yet, converging evidence is needed to demonstrate that the type of memory affected by HFS diet consumption is indeed hippocampus dependent. Moreover, the extent to which HFS diet can also affect executive functioning, and indirectly affect memory requires further examination. In this online study, we asked 349 young adults to report their HFS diet consumption and complete a word memory task, the Everyday Memory Questionnaire, and importantly two memory tasks that have been shown to robustly engage the hippocampus, i.e., the Pattern Separation and Associative Memory Tasks. Participants also completed two executive functioning tasks, the Trail Making Task (TMT) and the Stroop Task. These measures assess attention/cognitive flexibility and the ability to inhibit cognitive interference, respectively. After controlling for confounding variables, we found that participants who reported higher level consumption of a HFS diet performed worse on the Pattern Separation Task and that higher HFS intake was significantly associated with poorer TMT task performance and longer Stroop average reaction time (RT). TMT and Stroop RT scores indicative of reduced executive function also partially mediated the relationship between HFS diet and memory performance on the pattern separation task. Taken together, our results provide converging evidence that HFS diet may impair hippocampus-dependent memory. HFS diet may also affect executive functioning and indirectly impair memory function. The findings are consistent with human subject and animal studies and call for further investigations on the psychological and neural mechanisms underlying the dietary effects on cognitive processes.

Integrated sensing–memory–computing artificial tactile system based on force sensors and memristors

Recently, numerous artificial tactile systems have been developed to mimic human tactile, employing force sensors in combination with external memory and computing units. However, the separated architecture of force sensing, memory, and computing results in high power consumption and significant delays, which pose a significant challenge for the development of efficient artificial tactile systems. In this study, we propose an integrated sensing–memory–computing artificial tactile system (smcATS) consisting of a graphene–polystyrene microparticle (G-PsMp) force sensor and an Ag-Fe3O4-ITO memristor. The design of the Ag-Fe3O4-ITO memristor with cross-shaped electrodes addresses the issue of micrometer-scale electrodes in conventional memristors that cannot be directly connected to force sensors. Furthermore, the smcATS demonstrates excellent properties of switching, endurance, and resistance–retention. Based on this, we have developed a visualized smcATS with a resistance state visualization circuit, which can better mimic skin bruising caused by strong external forces. Most importantly, the smcATS can avoid the need for analog-to-digital conversion and data transfer between separate memory and computing units, providing an alternative perspective for developing more efficient artificial tactile systems.

Aversive memory conditioning induces fluoxetine-dependent anxiety-like states in the crab Neohelice granulata.

The interactions between memory processes and emotions are complex. Our previous investigations in the crab Neohelice led to an adaptation of the affective extension of sometimes opponent processes (AESOP) model. The model proposes that emotions generate separate emotive memory traces, and that the unfolding of emotional responses is a crucial component of the behavioral expression of reactivated memories. Here, we show that an aversive conditioning, that used changes in an innate escape response to an aversive visual stimulus, induced an emotional behavior that endured beyond the stimuli: the aversive memory training built an anxiety-like state evaluated in a dark/light plus-maze. We found that, after the training session, crabs displayed aversion to maze light areas, and an increased time immobilized in the dark zones of the maze, an anxiety-like behavior induced by stressors or physiological conditions in other crustaceans. The training-dependent anxiety-like behavior was blocked by pretraining administration of fluoxetine, suggesting an underlying serotonin-dependent phenomenon. We hypothesize that this training-induced anxiety-like state generates a separate emotive memory trace that is reinstated and crucial for the modulation of memory expression once the memory is reactivated.

Recursive Algorithm for Forming Structured Sets of Information Blocks that Increase the Speed of Performing Procedures for Determining Their Source

Purpose of research. The article examines the features of the synthesis of specialized devices that control the integrity and authenticity of individual information blocks based on CBC codes. Approaches aimed at reducing computational and resource costs when performing such procedures are considered. The dependencies between the performance indicators and the requirements for the volume of internal memory of specialized computers processing data in CBC mode are formulated..Methods. The implementation of data source authentication procedures using encoding in the mode of concatenation of individual data blocks is an effective method of increasing reliability in conditions of a limited size of verified authentication sequences. At the same time, its implementation in receivers requires the creation of specialized calculators that process tree-like structures that arise during data decoding, consisting of separate data blocks. To reduce resource and computational costs when processing such structures, indirect addressing is used, in which block data is stored in RAM, and their addresses are stored in the high-speed register memory of the computer itself.Results. A model of indirect addressing of data blocks in RAM has been created. Pointers to blocks are stored in a separate register memory and each pointer is placed according to the decoded sequence number of the block in the sequence. Each block address in RAM is supplemented by a set of pointers to subsequent blocks in the branches of the tree structure. The created mathematical model made it possible to estimate the size in bits of all the pointers involved and their number, which made it possible to determine the need for a computer processing a tree structure in register memory.Conclusion. The paper shows that using a combination of matrix and list organization of block address storage reduces the need for register memory of the calculator by 50-60%. At the same time, the computer can process the tree-like structure of information blocks using high-performance iterative algorithms, which would be impossible if only the list organization of address storage was used.

211 Subthalamic Nucleus Deep Brain Stimulation Engages Memory Networks in Patients With Parkinson’s Disease

INTRODUCTION: Parkinson’s disease (PD) patients with deep brain stimulation (DBS) implantation to the subthalamic nucleus (STN) often have neurocognitive side effects, but the modulated networks associated with their occurrence are largely unknown. METHODS: We localized electrodes and investigated brain connectivity seeding from stimulation volumes in patients that underwent subthalamic deep brain stimulation using a normative resting state functional connectome atlas composed of 1000 healthy subjects. Pre- and post-operative neuropsychological testing data was acquired before and after surgery using two similar memory paradigms (list recall and figure recall). The connectivity profiles associated with changes in these tests were calculated. Results were compared with automated meta-analysis maps calculated using neurosynth and neuroquery. RESULTS: 41 patients were included in the analysis. Positive functional connections between stimulation sites and medial temporal lobe, medial prefrontal cortex, and parieto-occipital region were associated with improvement in list recall. This connectivity profile showed robustness in a leave-one-out cross-validation (R = 0.32, p = 0.027). A similar connectivity profile was associated with figure recall improvement, also robust to cross-validation (R = 0.30, p = 0.019). The profiles associated with the two tasks were able to cross-estimate performance on the respective other task (R = 0.45, p = 0.008; R = 0.26, p = 0.045). When comparing these connectivity profiles with meta-analytic maps in the neurosynth database, the cognitive terms involved with memory showed highest improvement. The neuroquery database areas of predicted activation overlapped with the connectivity maps in the midbody and posterior hippocampal region. CONCLUSIONS: This retrospective study relates modulation of brain networks associated with memory processing with improvements in two separate memory tasks.

Paradoxical decrease of imitation performance with age in children.

Imitation development was studied in a cross-sectional design involving 174 primary-school children (aged 6-10), focusing on the effect of actions' complexity and error analysis to infer the underlying cognitive processes. Participants had to imitate the model's actions as if they were in front of a mirror ('specularly'). Complexity varied across three levels: movements of a single limb; arm and leg of the same body side; or arm and leg of opposite body sides. While the overall error rate decreased with age, this was not true of all error categories. The rate of 'side' errors (using a limb of the wrong body side) paradoxically increased with age (from 9 years). However, with increasing age, the error rate also became less sensitive to the complexity of the action. This pattern is consistent with the hypothesis that older children have the working memory (WM) resources and the body knowledge necessary to imitate 'anatomically', which leads to additional side errors. Younger children might be paradoxically free from such interference because their WM and/or body knowledge are insufficient for anatomical imitation. Yet, their limited WM resources would prevent them from successfully managing the conflict between spatial codes involved in complex actions (e.g. moving the left arm and the right leg). We also found evidence that action side and content might be stored in separate short-term memory (STM) systems: increasing the number of sides to be encoded only affected side retrieval, but not content retrieval; symmetrically, increasing the content (number of movements) of the action only affected content retrieval, but not side retrieval. In conclusion, results suggest that anatomical imitation might interfere with specular imitation at age 9 and that STM storages for side and content of actions are separate.

Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators

Image processing and machine learning applications benefit tremendously from hardware acceleration. Existing compilers target either FPGAs, which sacrifice power and performance for programmability, or ASICs, which become obsolete as applications change. Programmable domain-specific accelerators, such as coarse-grained reconfigurable arrays (CGRAs), have emerged as a promising middle-ground, but they have traditionally been difficult compiler targets since they use a different memory abstraction. In contrast to CPUs and GPUs, the memory hierarchies of domain-specific accelerators use push memories : memories that send input data streams to computation kernels or to higher or lower levels in the memory hierarchy and store the resulting output data streams. To address the compilation challenge caused by push memories, we propose that the representation of these memories in the compiler be altered to directly represent them by combining storage with address generation and control logic in a single structure—a unified buffer. The unified buffer abstraction enables the compiler to separate generic push memory optimizations from the mapping to specific memory implementations in the backend. This separation allows our compiler to map high-level Halide applications to different CGRA memory designs, including some with a ready-valid interface. The separation also opens the opportunity for optimizing push memory elements on reconfigurable arrays. Our optimized memory implementation, the Physical Unified Buffer, uses a wide-fetch, single-port SRAM macro with built-in address generation logic to implement a buffer with two read and two write ports. It is 18% smaller and consumes 31% less energy than a physical buffer implementation using a dual-port memory that only supports two ports. Finally, our system evaluation shows that enabling a compiler to support CGRAs leads to performance and energy benefits. Over a wide range of image processing and machine learning applications, our CGRA achieves 4.7× better runtime and 3.5× better energy-efficiency compared to an FPGA.

Endocytosis is required for consolidation of pattern-separated memories in the perirhinal cortex.

The ability to separate similar experiences into differentiated representations is proposed to be based on a computational process called pattern separation, and it is one of the key characteristics of episodic memory. Although pattern separation has been mainly studied in the dentate gyrus of the hippocampus, this cognitive function if thought to take place also in other regions of the brain. The perirhinal cortex is important for the acquisition and storage of object memories, and in particular for object memory differentiation. The present study was devoted to investigating the importance of the cellular mechanism of endocytosis for object memory differentiation in the perirhinal cortex and its association with brain-derived neurotrophic factor, which was previously shown to be critical for the pattern separation mechanism in this structure. We used a modified version of the object recognition memory task and intracerebral delivery of a peptide (Tat-P4) into the perirhinal cortex to block endocytosis. We found that endocytosis is necessary for pattern separation in the perirhinal cortex. We also provide evidence from a molecular disconnection experiment that BDNF and endocytosis-related mechanisms interact for memory discrimination in both male and female rats. Our experiments suggest that BDNF and endocytosis are essential for consolidation of separate object memories and a part of a time-restricted, protein synthesis-dependent mechanism of memory stabilization in Prh during storage of object representations.

Generalization and false memory in acquired equivalence

Memory allows us to remember specific events but also combine information across events to infer new information. New inferences are thought to stem from integrating memories of related events during encoding but can be also generated on-demand, based on separate memories of individual events. Integrative encoding has been argued as dominant in the acquired equivalence paradigm, where people have a tendency to assume that when two faces share one preference, they also share another. A downside may be a loss of source memory, where inferred preferences are mistaken for observed ones. Here, we tested these predictions of the integrative encoding hypothesis across five datasets collected using variations of the acquired equivalence paradigm. Results showed a statistically reliable but numerically small tendency to generalize preferences across faces, with stronger evidence for on-demand inferences at retrieval rather than spontaneous integration during encoding. A newly included explicit source memory test showed that participants differentiated learned from inferred preferences to a high degree, irrespective of whether they generalized preferences across faces. False memory was however increased in participants who made generalization decisions faster, which could be consistent with integrative encoding and/or source monitoring frameworks. The results suggest that generalization in acquired equivalence may result from integrated representations that facilitate new inferences at the expense of source memory, but also demonstrate that on-demand retrieval-based processes may play a larger role in this paradigm than previously thought. Finally, the results indicate that reaction times may be more sensitive than performance as a means to assess representations underlying behavior. More broadly, the study informs current theories of generalization and knowledge representation and provides new insights into how memory biases decisions.

MPEG/H256 video encoder with 6T/8T hybrid memory architecture for high quality output at lower supply

The use of Multimedia video content is increased rapidly in the past decade, and most multimedia video content is used by mobile phone users. Multimedia video processing consumes significant power during video compression, and thus low power multimedia video compression is essential for battery operated devices. Moving Picture Experts Group (MPEG) Video encoding is giving a higher compression rate and low bandwidth requirement. Conventional MPEG Video encoding architecture uses the conventional 6T memory cells to store video frames for further compression processing. The failure probability of 6T cells is significantly large (0.0988 at 600 mV supply voltage), leading to a decrease in the output quality of the encoded video. From the hybrid memory matrix formulation, it is calculated that storing higher-order MSB bits in highly stable memory cells will provide high-quality video encoding processing as compared to the conventional technique because the human eye is more susceptible to higher-order luminance bits. Hence, in this research work instant of using conventional 6T memory cells during video encoding processing, a unique Hybrid 6T/8T memory architecture is proposed, where the 8-bit Luminance pixels are stored favourably in consonance with their effect on the output quality. The higher order luminance bits (MSB’s) require high stability and thus these bits are stored in the 8T bit cells and the remaining bits (LSB’s) are stored in the conventional 6T bit cells for high-quality video encoding processing. This research article also proposes a separate memory peripheral circuitry for hybrid memory architecture for video encoding techniques. In addition, this article proposes a unique architecture for parallel video processing with the use of a hybrid pixel memory array. The failure probability of 6T and 8T at the worst failure corner (FS corner for read and SF corner for write) is simulated for 30000 Monte-Carlo simulations points at 45 nm CMOS technology node using CADENCE EDA tool. For the simulation work here, a standard Common Intermediate Format/Quarter Common Intermediate Format (CIF/QCIF) Coastguard video sample is used and for output quality here average PSNR method is used and simulation work is performed using the MATLAB tool.The worst PSNR for conventional 6T memory array and Hybrid memory array at 600 mV supply voltage shows improvement in worst minimum PSNR as 6.43 dB is calculated. 30% less power consumption to conventional memory architecture.