Sentaurus Technology Computer-aided Design Research Articles

Aggravated NBTI reliability due to hard-to-detect open defects

FinFET technology has become an attractive candidate for high-performance and power-efficient applications. In the other hand, the behavior of FinFET devices is influenced by self-heating effect (SHE) due to its 3D structure, low thermal coupling and quantum confinement effect, among others. SHE degrades the device’s performance and could worsen reliability mechanisms like NBTI. In addition, some hard-to-detect open defects in FinFET based-circuits using logic gates designed with multi-fin and multi-finger techniques may escape the test and present abnormal static currents, which may increase the impact of self-heating effect and make the NBTI degradation more severe. Hence, it is crucial to accurately determine the temperature profiles of those chips passing the test and presenting abnormal static currents. This paper investigates the reliability of chips passing the test with abnormal static currents using Sentaurus Technology Computer-Aided Design (TCAD). FinFET transistors are calibrated with Intel 14-nm FinFET technology. Our TCAD simulation framework determines accurately the temperature and NBTI degradation. Using the TCAD information, the device degradation over time can be predicted. Moreover, the delay penalization of a critical logic path of an ISCAS benchmark circuit is investigated. The delay penalization of logic paths, attributed to the defect and NBTI, is analyzed with varying logic depths, emphasizing the importance of addressing critical paths with different logic depths. Our study leads to new considerations for improving the prediction of circuit reliability and taking countermeasures.

Damage Effects and Mechanisms of High-Power Microwaves on Double Heterojunction GaN HEMT

In this paper, simulation modeling was carried out using Sentaurus Technology Computer-Aided Design. Two types of high electron mobility transistors (HEMT), an AlGaN/GaN/AlGaN double heterojunction and AlGaN/GaN single heterojunction, were designed and compared. The breakdown characteristics and damage mechanisms of the two devices under the injection of high-power microwaves (HPM) were studied. The variation in current density and peak temperature inside the device was analyzed. The effect of Al components at different layers of the device on the breakdown of HEMTs is discussed. The effect and law of the power damage threshold versus pulse width when the device was subjected to HPM signals was verified. It was shown that the GaN HEMT was prone to thermal breakdown below the gate, near the carrier channels. A moderate increase in the Al component can effectively increased the breakdown voltage of the device. Compared with the single heterojunction, the double heterojunction HEMT devices were more sensitive to Al components. The high domain-limiting characteristics effectively inhibited the overflow of channel electrons into the buffer layer, which in turn regulated the current density inside the device and improved the temperature distribution. The leakage current was reduced and the device switching characteristics and breakdown voltage were improved. Moreover, the double heterojunction device had little effect on HPM power damage and high damage resistance. Therefore, a theoretical foundation is proposed in this paper, indicating that double heterojunction devices are more stable compared to single heterojunction devices and are more suitable for applications in aviation equipment operating in high-frequency and high-voltage environments. In addition, double heterojunction GaN devices have higher radiation resistance than SiC devices of the same generation.

Modeling and Bulk Characterization of 4HSIC Radiation Detector in Sentaurus TCAD Simulation Environment

This paper gives an insight into the need for radiation detection and the most commonly flexible and efficient radiation detector. It also examines bulk characteristics of 4H-SiC semiconductor radiation detector with Ni and Ti as metals for the contact. Bulk characterization of the device, including: doping concentration, electrons and holes behaviors, space charge and current densities were carried out. The modeling is conducted using Sentaurus Technology Computer Aided Design (TCAD) to examine charge transport in bulk 4HSiC material. Data obtained were further analyzed through Sentaurus visual, sentaurus Techplot and Excel to clearly determine the characteristics of the device. It is observed that when the semiconductor and metal are in contact, the Fermi-level is established where the doping concentration varied with either magnitude of the doping concentration or nature of the dopant. Similarly, Schottky and ohmic contacts and temperature effect were observed from the device characteristics which demonstrate that, the detector can withstand a temperature from the range of 100K to 700K in no fluctuating state.

GaN-HEMT Performance Enhancement

In this work, a simulation analysis and calibration are carried out to improve the performance of AlGaN/GaN- MOSHEMTs (Metal-Oxide Semiconductor High Electron Mobility Transistors). The effect of the AlGaN layer thickness, gate length, Al mole fraction, and the interface traps on the electrical performance of the device has been presented. Device simulations have been done using Sentaurus technology computer-aided design (TCAD). The simulations and analysis show better drain current, transconductance, and cut-off frequency performance. The maximum cut-off frequency shown by the proposed HEMT device is 45.7 GHz at 100-nm gate length. Good transcoductance has been obtained by scaling down the gate length of the device, which is ascribed to the present two-dimensional electron gas (2DEG) density that supports upgrading the output current. Higher drain current is achieved without using acceptor-like traps in the Al2O3/AlGaN interface. Results show that the Al2O3/AlGaN/GaN-based MOSHEMT is a promising device for high-frequency and power electronic applications.

Double-gated ferroelectric-gate field-effect-transistor for multi-bit content-addressable memories

In this study, we proposed a novel multi-bit content addressable memory (MCAM) cell based on one single double-gated ferroelectric-gate FET (DG-FeFET). Baseline DG-FeFET has been modeled, and the parameters are calibrated with experimental results by technology computer aided design (TCAD). Thanks to the pairing opposite ferroelectric states of the top/bottom gate (TG/BG) and pairing opposite searching voltages applied to TG and BG, MCAM functions with one DG-FeFET can be realized. The corresponding writing and searching operations are investigated in detail by the TCAD Sentaurus model. In addition, it is clarified that reducing the coupling effect of top and bottom channel by appropriately increasing the body thickness (Tbody) can boost the mismatch/match ratio. The proposed MCAM cell with one single DG-FeFET is promising for ultra-high-density computing systems.

TCAD simulations of internal amplification in high purity germanium detectors

Simulations of internal amplification processes in high purity germanium (HPGe) detectors for gamma radiation are presented. The Synopsys Sentaurus Technology Computer-Aided Design (TCAD) package was employed to study conditions favourable to charge multiplication within volume of the detector. The physics model was developed, and validated where possible against known results from existing literature. The model was then applied to a new detector and a systematic study of the measurable parameters influencing charge collection and electric field profile was performed. Evidence of the internal amplification in the developed HPGe detector model was demonstrated at 4 kV bias voltage with anode diameter below 100 μm, corresponding to 16 kV/cm electric field and when an additional dopant with concentrations >5×1010cm−3 under the anode implanted. These effects were also simulated and observed in silicon detectors, giving additional confidence in the validity of the findings for germanium, presented in this work.

TCAD Simulation Models, Parameters, and Methodologies for β-Ga2O3 Power Devices

β-Ga2O3 is an emerging material and has the potential to revolutionize power electronics due to its ultra-wide-bandgap (UWBG) and lower native substrate cost compared to Silicon Carbide and Gallium Nitride. Since β-Ga2O3 technology is still not mature, experimental study of β-Ga2O3 is difficult and expensive. Technology-Computer-Aided Design (TCAD) is thus a cost-effective way to study the potentials and limitations of β-Ga2O3 devices. In this paper, TCAD parameters calibrated to experiments are presented. They are used to perform the simulations in heterojunction p-NiO/n-Ga2O3 diode, Schottky diode, and normally-off Ga2O3 vertical FinFET. Besides the current-voltage (I-V) simulations, breakdown, capacitance-voltage (C-V), and short-circuit ruggedness simulations with robust setups are discussed. TCAD Sentaurus is used in the simulations but the methodologies can be applied in other simulators easily. This paves the road to performing a holistic study of β-Ga2O3 devices using TCAD.

Sensitivity assessment of dielectric modulated GaN material based SOI-FinFET for label-free biosensing applications

Abstract This work presents the sensitivity assessment of gallium nitride (GaN) material-based silicon-on-insulator fin field effect transistor by dielectric modulation in the nanocavity gap for label-free biosensing applications. The significant deflection is observed on the electrical characteristics such as drain current, transconductance, surface potential, energy band profile, electric field, sub-threshold slope, and threshold voltage in the presence of biomolecules owing to GaN material. Further, the device sensitivity is evaluated to identify the effectiveness of the proposed biosensor and its capability to detect the biomolecules with high precision or accuracy. The higher sensitivity is observed for Gelatin (k = 12) in terms of on-current, threshold voltage, and switching ratio by 104.88%, 82.12%, and 119.73%, respectively. This work is performed using a powerful tool, three-dimensional (3D) Sentaurus Technology computer-aided design using a well-calibrated structure. The results pave the way for GaN-SOI-FinFET to be a viable candidate for label-free dielectric modulated biosensor applications.

Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors

In this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generation nano-device. To extract data reflecting the accurate physical characteristics of NSFETs, the Sentaurus TCAD (technology computer-aided design) simulator was used. The proposed ANN model accurately and efficiently predicts currents and capacitances of devices using the five proposed key geometric parameters and two voltage biases. A variety of experiments were carried out in order to create a powerful ANN-based compact model using a large amount of data up to the sub-3-nm node. In addition, the activation function, physics-augmented loss function, ANN structure, and preprocessing methods were used for effective and efficient ANN learning. The proposed model was implemented in Verilog-A. Both a global device model and a single-device model were developed, and their accuracy and speed were compared to those of the existing compact model. The proposed ANN-based compact model simulates device characteristics and circuit performances with high accuracy and speed. This is the first time that a machine learning (ML)-based compact model has been demonstrated to be several times faster than the existing compact model.

Stacked ferroelectric heterojunction tunnel field effect transistor on a buried oxide substrate for enhanced electrical performance *

The device behavior of a stacked ferroelectric heterojunction tunnel field effect transistor (Fe-HTFET) on a buried oxide substrate is investigated in this paper. Si-doped HfO2 was taken as the ferroelectric material over an oxide layer (gate dielectric) in a stacked gate configuration. A higher drive current and reduced subthreshold swing (SS) may be achieved using Si-doped HfO2 that amplifies the gate bias. The effect of various electrical parameters has been investigated by changing the geometric dimensions of the proposed device. The dimensional parameters have been optimized after extensive simulations. The proposed Fe-HTFET simulations and results show that this structure boosts performance significantly and could be considered a good candidate for ultra-low-power applications. To investigate the performance of the proposed Fe-HTFET, two-dimensional simulations have been done using the Sentaurus technology computer-aided design tool.

Effects of Symmetric and Asymmetric Double-Layer Spacers on a Negative-Capacitance Nanosheet Field-Effect Transistor

The effect of three double-layer spacers (corner/selective/dual) on the performance of a negative-capacitance nanosheet field-effect transistor (NC-NSFET) was investigated for the first time. Sentaurus technology computer-aided design simulations revealed that the NC-NSFET with corner spacer will be significantly improved in transfer and high frequency characteristics due to the increase of ferroelectric layer thickness, and the NC-NSFET with a selective spacer structure exhibits better gate controllability. Compared with the ordinary dual-k spacer structure, the switching current ratio is doubled, and its subthreshold swing and drain-induced barrier lowering are reduced by 3.0% and 48%, respectively. In addition, by introducing a selective spacer at the source side and a corner spacer at the drain side, the NC-NSFET has a smaller intrinsic delay and exhibits better capacitance matching and stronger gate controllability than that with a symmetric spacer. For the double-layer spacer, the extension of the high-k spacer in the horizontal direction is more beneficial to the improvement of the device performance than that in the vertical direction, which provides a more comprehensive reference for the spacer application in NC-NSFET.

DC and RF analysis of vertical 3D p-type silicon nanotube FET for low power applications

ABSTRACT A vertical p-type 3D silicon nanotube field effect transistor (p-type Si-NTFET) is designed and simulated by using the tool Sentaurus Technology computer-aided design (TCAD). To improve the performance with reduced short channel effects, Si-NTFET device is created with inner and outer gate structures. The performance of the proposed device is analysed in terms of outer gate length. The vertical 3D p-type Si-NTFET gives an on state current (I ON) of −2.084 × 10−3 A/µm, off state current of (I OFF) of −2.457 × 10−12A/µm and subthreshold swing of the p-type Si-NTFET device is 53 mV/dec at V DS of −0.3 V. The obtained I ON/I OFF ratio of the device is 109. The capacitances (C GD, C GG) and the transconductance (g m) and cutoff frequency (f t) of the device are also analysed. The simulated p-type Si-NTFET device has proved that the device is suitable for low-power applications.

Improvement in Turn-Off Loss of the Super Junction IGBT with Separated n-Buffer Layers.

In this study, we propose a super junction insulated-gate bipolar transistor (SJBT) with separated n-buffer layers to solve a relatively long time for carrier annihilation during turn-off. This proposition improves the turn-off characteristic while maintaining similar on-state characteristics and breakdown voltage. The electrical characteristics of the devices were simulated by using the Synopsys Sentaurus technology computer-aided design (TCAD) simulation tool, and we compared the conventional SJBT with SJBT with separated n-buffer layers. The simulation tool result shows that turn-off loss (Eoff) drops by about 7% when on-state voltage (Von) and breakdown voltage (BV) are similar. Von increases by about 0.5% and BV decreases by only about 0.8%.

Studying the Effect of Light Incidence Angle on Photoelectric Parameters of Solar Cells by Simulation

It is crucial to examine the dependence of photoelectric parameters of solar cells on the light incidence angle. In the present study, two solar cell models have been developed using the Sentaurus Technology Computer-Aided Design software package. The light spectrum AM1.5 has been directed on the frontal surface of solar cells at different angles. It has been found that the angular coefficient of the photoelectric parameters of a solar cell with nanoparticles included, is two times more than that of a simple solar cell. Besides, it has been found that the efficiency of platinum nanoparticles induced solar cells is 2.15 times greater than simple solar cell efficiency. When the light incidence angle has been varied from 0 to 60 degrees, the short-circuit current has changed by 11% for simple solar cells and by 10% for solar cells with nanoparticles. Further, it has been observed that the variation of power for simple solar cells is 12.5%, while it is 10.5% for solar cells with nanoparticles. In addition, the short-circuit current of solar cells with nanoparticles has been found to be linear within a light incidence angle ranging from 0 to 60 degrees.

Influence of Graded AlGaN sub-channel over the DC and Breakdown characteristics of a T-gated AlGaN/GaN/AlInN MOS-HEMT

The impact of graded Al0.05Ga0.95N sub-channel over the DC characteristics of AlGaN/GaN/AlInN Metal Oxide Semiconductor-High Electron Mobility Transistor (MOS-HEMT) has been investigated here. By placing a field plate over the gate region and forming a T-gated structure, the breakdown characteristics are examined using Sentaurus Technology Computer-Aided Design (TCAD) simulation tool. An analytical study is carried out into the evaluation of various device parameters like drain current, transconductance and threshold voltage. RF parameters like cut-off frequency and gain has also been examined. Various physical models such as hydrodynamic, thermodynamic, piezoelectric polarization, impact ionization models are considered. HfO2 as an oxide layer directly influences the charge confinement near the Two-Dimensional Electron Gas (2DEG), thereby causing a positive shift in the threshold voltage of the device. T-gated formation of the gate helped in enhancing the breakdown voltage of the device to nearly 750 V. A maximum current drive of 1.79 A/mm mm was obtained for the proposed device, nearly 24% improvement from the conventional Composite-channel (CC) HEMT. The current outcomes and the produced frequency characteristics determines the linearity enhancement occurred in the device, caused due to the graded AlGaN sub-channel below the GaN channel layer. The trade-off between specific on-resistance and breakdown voltage is well preserved by employing a T-gated structure with low normal gate length. The outcomes prove the device to be a prime contender for high power switching as well as large signal applications.

A 4H-SiC merged P–I–N Schottky with floating back-to-back diode

A novel 4H-SiC merged P–I–N Schottky (MPS) with floating back-to-back diode (FBD), named FBD-MPS, is proposed and investigated by the Sentaurus technology computer-aided design (TCAD) and analytical model. The FBD features a trench oxide and floating P-shield, which is inserted between the P+/N– (PN) junction and Schottky junction to eliminate the shorted anode effect. The FBD is formed by the N-drift/P-shield/N-drift and it separates the PN and Schottky active region independently. The FBD reduces not only the V turn to suppress the snapback effect but also the V on at bipolar operation. The results show that the snapback can be completely eliminated, and the maximum electric field (E max) is shifted from the Schottky junction to the FBD in the breakdown state.

CMOS Pixel Potentials Extraction Method From Test Structures Based on EKV Model

Knowing exactly potentials' distribution in pixels is a key to ensure that electron retention and transport enable a good pixel operation. Moreover, it is also a key parameter for control of charge storage capability or full-well capacity, strongly driven by potential barriers. In this article, a new method is presented to characterize potentials within pixels from test structure measurements. The proposed method enables to extract potential under a gate, pinning potential of photodiodes or memories, and any potential along the charge path. It is based on the use of the Enz-Krummenacher-Vittoz (EKV) model together with measurements on adequate test structures. Thanks to the so-called “ Y function series resistance correction,” the method can even be applied to test structures including devices in series as in real pixel. The method proposed here is assessed using Sentaurus technology computer-aided design (TCAD) simulation results. Such potentials extracted on the test structure can be used for process and pixel developments, device monitoring, reliability studies, and TCAD calibration.

Charge Plasma-Based Phosphorene Tunnel FET Using a Hybrid Computational Method

In this paper, a charge plasma-based phosphorene double-gate tunnel FET (CP-BPDGTFET) is investigated. A hybrid simulation technique involving both atomistic and technology computer-aided design (TCAD) has been used to simulate the device characteristics. First, the density functional theory has been used to simulate phosphorene electrical characteristics (monolayer to few-layer, including armchair and zigzag directions). The parameters such as band gap and effective mass obtained using an atomistic simulator tool are exported into Sentaurus TCAD to simulate the device characteristics. The drain current characteristics are calibrated for conventional double gate phosphorene tunnel FET with non-equilibrium Green's function results. The DC characteristics of the proposed device are studied. The device performance is analysed by varying the device parameters such as gate length (Lg), spacer length (Ls), and gate workfunction (ϕm). Based on the study, an optimised device is designed, and its characteristics are obtained. The optimised device offers an on-current value of 405 µA/µm, SS = 79 mV/dec, Ion/Ioff = 1.13 × 106 for 30 nm gate length. It establishes that CP-BPDGTFET is a suitable candidate for energy-efficient circuit applications.

Analysis of black phosphorus double gate MOSFET using hybrid method for analogue/RF application

In this work, the authors study the performance of black phosphorus double gate MOSFET (BP-DGMOSFET) within the ballistic limit. A hybrid simulation technique involving both atomistic and technology computer-aided design (TCAD) tool has been used for the first time to simulate the device characteristics. First, the density functional theory has been used to simulate the electrical characteristics of single and fewlayer (five layers) phosphorene (including armchair and zigzag directions). The parameters such as bandgap and effective mass obtained using an atomistic simulator tool are exported into Sentaurus TCAD to simulate the BP-DGMOSFET characteristics. They have used the kinetic velocity model and quantum model to account for the ballistic mobility and quantum effects in the device. The current drain characteristics are calibrated with non-equilibrium Greens function (NEGF) simulation and radio frequency (RF) characteristics with compact model values and found that their results agree with them. Secondly, the other RF figure of merits, such as maximum frequency of oscillation, transconductance, output conductance and stability has also been simulated. It is found that their proposed method shows results comparable to NEGF with reduced computation time and complexity.

Origins of Soft-SwitchingCossLosses in SiC Power MOSFETs and Diodes for Resonant Converter Applications

The recent development and commercialization of wide bandgap (WBG) power semiconductors, specifically gallium nitride (GaN) and silicon carbide (SiC), have driven the increase in switching frequency for soft-switching power converters, such as the Class E, Class Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and Class DE resonant inverters and rectifiers. However, prior literature has characterized numerous commercial GaN and SiC devices using the Sawyer-Tower circuit and discovered significant large-signal C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> oss</sub> charge-voltage hysteresis. This C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> oss</sub> hysteresis, equivalent to OFF-state energy loss, is highly dependent on the frequency and voltage across the device, hindering the efficiency and performance of MHz-range soft-switched converters. This article is the first to explain the origin of the C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> oss</sub> loss in SiC power devices as charging and discharging conduction losses at the termination of the device. The loss characteristics relative to the operating voltage, frequency, dV/dt, and temperature are dictated by incomplete ionization. Incomplete ionization also highlights a significant inconsistency between the large-signal C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> oss</sub> behavior and small-signal behaviors, which is often the model used in manufacturers' datasheets and SPICE simulations. The large-signal charge-voltage behavior is transient, where the charge in C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> oss</sub> depends on the rate of the voltage swing across the device. We validate these hypotheses through mixed-mode simulations using the Sentaurus technology computer-aided design (TCAD) and experimentally using commercial and custom SiC devices.