CMOS Pixel Potentials Extraction Method From Test Structures Based on EKV Model

Abstract

Knowing exactly potentials' distribution in pixels is a key to ensure that electron retention and transport enable a good pixel operation. Moreover, it is also a key parameter for control of charge storage capability or full-well capacity, strongly driven by potential barriers. In this article, a new method is presented to characterize potentials within pixels from test structure measurements. The proposed method enables to extract potential under a gate, pinning potential of photodiodes or memories, and any potential along the charge path. It is based on the use of the Enz-Krummenacher-Vittoz (EKV) model together with measurements on adequate test structures. Thanks to the so-called “ Y function series resistance correction,” the method can even be applied to test structures including devices in series as in real pixel. The method proposed here is assessed using Sentaurus technology computer-aided design (TCAD) simulation results. Such potentials extracted on the test structure can be used for process and pixel developments, device monitoring, reliability studies, and TCAD calibration.