Semi-formal Method Research Articles

ReqNet and ReqSim: A Network and Semantic Similarity Dataset of Requirements from the Tree Structure of System Requirement Specifications

Abstract Systems are developed as a solution to the problem space defined by their requirements. The requirements are acquired during the elicitation process. The creative nature of the elicitation process, proprietary nature of requirements, the need of extensive preprocessing and the diverse techniques for analysis restricts the development of a requirement dataset. There exists no standard method to create a requirement dataset. Thus, we devise a semi-formal method to create a multi-purpose requirement dataset that harnesses human knowledge in the system requirement specification documents (SyRSDs) to facilitate the deployment of modern computing algorithms. Our dataset has three forms. (1) ReqList, a list of requirements from 86 distinct systems with their document structure in pure text form. The 12701 requirements are ready to leverage natural language processing techniques and unsupervised machine learning techniques. (2) ReqNet, a large network of requirements consisting of 17375 nodes to deploy graph-theoretic algorithms for requirement engineering. ReqNet portrays small-world network characteristics with an average distance of 9.5619 links. (3) ReqSim, a dataset consisting of 10933 pairs of requirements annotated with their similarity scores. ReqSim enables sentence-level supervised learning tasks to exploit the semantics of requirements. The similarity scores are coherent with human knowledge. Our dataset is grounded by the tree structure of SyRSDs. We devise a method to extract a tree from the SyRSDs. The tree structure resonates with the hierarchical nature of the requirement allocation process. The ReqList, ReqNet and ReqSim dataset is available at https://github.com/ChandanKSahu/ReqList_ReqNet_ReqSim.

Template-Based Semi-Formal Approach to Robust Equivalence Checking

In order to ensure the correct behaviors and that bugs have not entered the design, equivalence checking technology plays an important role in VLSI design. In this paper, we propose a new template-based, semi-formal equivalence checking method for C-based system design and Register Transfer Level (RTL)/netlist implementation design, whose internal structures can be very different. Staring with a C-based description as a specification, we first randomly generate a set of templates. Each template has one or a small number of missing sentences based on the original C description. Many sets of mutants can be represented by these templates, using symbolic constants, variables, and operators. The process of finding those missing portions can be formulated as a Quantified Boolean Formula (QBF) problem. Then, based on the counter-example guided method, by simulating only the implementation, the templates can be refined. Since the templates are generated from the original C description, their structures are very similar to each other. With the original C description as a specification, we can simulate or formally check the equivalence between the refined template and the original C description, thereby indirectly achieving the equivalence checking of the C-based systems design and RTL/netlist implementation design. The experimental results on several practical examples demonstrate the effectiveness of the proposed method.

A Specification-Based Semi-Formal Functional Verification Method by a Stage Transition Graph Model

The semi-formal verification method, in which the functionality is formally specified and the checking is undertaken through the formal model-based simulation, has been a promising choice for the functional verification of hardware designs. The existing methods derive the formal model from design implementation. This causes poor scalability and practicality. A more feasible solution is to derive the formal model directly from the specification. In this paper, we propose a specification-based semi-formal method for functional verification. The proposed semi-formal method uses a stage transition graph (STG) model to formally describe the function points in the specification. Meanwhile, we propose an automatic test pattern generation (ATPG) method to generate the test vectors based on the STG model. The proposed STG-based ATPG method can reach possible corner cases and ensure exhaustive exploration of functionality for both control-dominated designs and data-dominated designs. Moreover, we develop an STG-based tool for automatic verification. Our experiments show that our method can automatically verify the functional correctness from the specification while achieving similar code coverage as implementation-based semi-formal approaches.

Simulation-Based Hardware Verification with a Graph-Based Specification

Simulation-based verification continues to be the primary technique for hardware verification due to its scalability and ease of use; however, it lacks exhaustiveness. Although formal verification techniques can exhaustively prove functional correctness, they are limited in terms of the scale of their design due to the state-explosion problem. Alternatively, semiformal approaches can involve a compromise between scalability, exhaustiveness, and resource costs. Therefore, we propose an event-driven flow graph-based specification, which can describe the cycle-accurate functional behaviors without the exploration of whole state space. To efficiently generate input sequences according to the proposed specification, we introduce a functional automatic test pattern generation (ATPG) approach, which involves the proposed intelligent redundancy-reduction strategy to solve problems of random test vectors. We also proposed functional coverage criterion based on the formal specification to support a more reliable measure of verification. We implement a verification platform based on the proposed semiformal approach and compare the proposed semiformal approach with the constrained randomized test (CRT) approach. The experiment results show that the proposed semiformal verification method ensures a more exhaustive and effective exploration of the functional correctness of designs under verification (DUVs).

Semi-formal method for security policies and design specifications

Semi-formal method for security policies and design specifications

Formal Philosophy and Legal Reasoning: The Validity of Legal Inferences

The aim of the present paper is to introduce a method to test the validity of legal inferences. We begin by presenting the rationale of our method and then we expose the philosophical foundations of our analysis. If formal philosophy is to be of help to legal discourse, then it must first reflect upon the law's fundamental characteristics that should be taken into account. Our analysis shows that (Canadian) legal discourse possesses three fundamental characteristics which ought to be considered if one wants to represent the formal structure of legal arguments. These characteristics are the presupposed consistency of legal discourse, the fact that there is a hierarchy between norms and obligations to preserve this consistency and the fact that legal inferences are subjected to the principle of deontic consequences. We present a formal deontic logic which is built according to these characteristics and provide the completeness results. Finally, we present a semi-formal method (based on the proposed deontic logic) to test the validity of legal inferences. This paper contributes to the literature insofar as it provides a method that covers a portion of the intuitive validity of legal inferences which is not covered by other frameworks.

Analyze the Mode Transition Logic of Automatic Flight Control System using Semi-Formal Approach

Autopilot system is a highly critical avionics system in modern aircraft as it steers the aircraft automatically. The autopilot is a highly complex system driven by a complex logic and is one of the major reasons for the accidents in automated airliner. The autopilot logic consists of the mode-transition logic which in automated mode steers the aircraft based on the aircraft aerodynamics. In the automated mode the correct and efficient working of the modetransition is highly critical; hence a high assurance approach is required to analyze the logic for its functionality and performance. In this paper, we present a semi-formal method based approach to analyze and validate the Mode-Transition Logic (MTL) for an indigenously developed commercial aircraft in the vertical and lateral directions. The MTL is analyzed and validated for its correct, complete, and reliable functionality and operation using Stateflow. The modeled MTL logic is validated for the allowed transitions based on the input combinations against the requirements for functionality and safety. The outcome of the approach shows encouraging results with respect to assurance in functionality, performance and safety in comparison to the conventional manual approach of testing. Similar semiformal based approach can be used to reduce the design effort in the design and development of complex system designs as compared to the manual analysis.

TOWARDS A FORMAL METHOD FOR THE TRANSFORMATION OF ONTOLOGY AXIOMS TO APPLICATION DOMAIN RULES

Ontologies in nowadays are widely used in the process of development of modern information systems (IS), since they are suitable to represent application domain knowledge. However, some aspects of ontology-based IS required to be developed. We propose a formal method for ontology axioms transformation into application domain rules, making them an important and integral part of each application domain and used to constrain or direct different aspects of business. Such rules can be consecutively transformed into an executable form and implemented in a software system of an IS. We propose to use the Z notation for formalisation of previously authors’ introduced ontology-based semi-formal method for development of application domain rules.

Translating STATEMATE models into FNLOG for the verification of safety requirements in reactive systems

In this paper, the authors explore the usefulness of a combination of semi-formal and formal methods in specifying reactive systems and verifying their properties. The authors propose an approach combining STATEMATE and the temporal logic FNLOG. STATEMATE is a semi-formal method, which has been used for the development of large industrial applications. It pertains to the specification and design of complex reactive systems and builds simulations and prototypes rapidly. Though STATEMATE provides rigorous specifications, these are not verifiable to ensure and guarantee the reliability of the system being developed. To fulfil the verification objective, a STATEMATE specification is translated into a logic based specification language FNLOG, which allows its verification. This paper describes the cross reference between STATEMATE and FNLOG features. Systematic derivation schemes from STATEMATE models to FNLOG specifications and different steps of the proposed translation procedure.

UML in Automation

Automation devices, which are based on digital information processing fulfilling functions in a distributed system are an increasing market area. This increases the requirements on the software of the communication controller of the devices. UML as a semi-formal method can provide new implementation and testing methods in this area. This paper gives an overview about the use of UML in nearly all steps of the V model development process.

UML Specification and Development of Safety-Relevant Industrial Communication Systems

Automation devices fulfilling functional safety is an increasing market area. Therefore methods for the software development are needed which fulfil these requirement. The V model and UML as a semi-formal method can provide support for the implementation and testing of dependable software in this area. This paper gives an overview about a safety related software development process using the example of safety fieldbus communication provided by PROFIBUS.