Abstract
Simulation-based verification continues to be the primary technique for hardware verification due to its scalability and ease of use; however, it lacks exhaustiveness. Although formal verification techniques can exhaustively prove functional correctness, they are limited in terms of the scale of their design due to the state-explosion problem. Alternatively, semiformal approaches can involve a compromise between scalability, exhaustiveness, and resource costs. Therefore, we propose an event-driven flow graph-based specification, which can describe the cycle-accurate functional behaviors without the exploration of whole state space. To efficiently generate input sequences according to the proposed specification, we introduce a functional automatic test pattern generation (ATPG) approach, which involves the proposed intelligent redundancy-reduction strategy to solve problems of random test vectors. We also proposed functional coverage criterion based on the formal specification to support a more reliable measure of verification. We implement a verification platform based on the proposed semiformal approach and compare the proposed semiformal approach with the constrained randomized test (CRT) approach. The experiment results show that the proposed semiformal verification method ensures a more exhaustive and effective exploration of the functional correctness of designs under verification (DUVs).
Highlights
Functional verification is the process that ensures conformance of a design under verification (DUV) to its specification
To efficiently generate input sequences according to the proposed specification, we introduce a functional automatic test pattern generation (ATPG) approach, which involves the proposed intelligent redundancy-reduction strategy to solve problems of random test vectors
We introduce a functional ATPG approach to efficiently generate input sequences according to the proposed specification
Summary
Functional verification is the process that ensures conformance of a design under verification (DUV) to its specification. In formal verification, an engine exhaustively exploits the state space of the design to prove the functional properties. A practical choice is semiformal verification, in which the specification of design functionality is formally completed and checking is undertaken through simulation. Semiformal verification avoids the state-explosion problem due to the absence of exploiting the whole state space It improves the degree of automation in generating test vectors and checking functional correctness. The equality of test-space distribution and the coverage of corner cases are two problems of random test vectors To solve these two problems, we categorize the input ports into data-path ports and control-path ports. We define functional coverage based on the proposed specification, and it ensures that the coverage of design functionality provided by vectors is measured. Compared with traditional code coverage, the proposed functional coverage supports a more reliable measure in the simulation process
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