Semiconductor Wafer Fabrication Research Articles

A simulated annealing algorithm for integration of shop floor control strategies in semiconductor wafer fabrication

The semiconductor manufacturing industry is one of the most important industries in Taiwan. Wafer fabrication is an essential process in semiconductor manufacturing. However, controlling the production system on the shop floor is extremely difficult owing to the complicated manufacturing process and reentrant characteristics. In this paper, the shop floor control (SFC) integration strategies (order review/release, dispatching, and rework strategies) in wafer fabrication are considered with using several performances. We reviewed the literature on SFC strategies in wafer fabrication. The proposed combination simulation and simulated annealing (SA) algorithm is presented for SFC strategies in wafer fabrication. The objective was to seek the near global optimum solution for the combination of SFC strategies for a specific performance indicator. From the results, the proposed methodology was found to perform well for combinations of SFC strategies using different performance indicators in wafer fabrication. However, no single combination of SFC strategies could satisfy all performance indicators. Hence, considering the trade-off among these production control strategies, a suitable strategy should be chosen based on the system control tactics. Considerable computational time was saved in this research.

Simplification methods for accelerating simulation-based real-time scheduling in a semiconductor wafer fabrication facility

This paper presents a real-time scheduling methodology in a semiconductor wafer fab that produces multiple product types with different due dates. In the suggested real-time scheduling method, lot scheduling rules and batch scheduling rules are selected from sets of candidate rules based on information obtained from discrete event simulation. Since a rule combination that gives the best performance may vary according to the states of the fab, a selected rule combination is employed for a certain period of time and then a new combination is selected and employed. Since multiple simulation runs should be made in the simulation-based real-time scheduling (SBRTS) method, it may take excessively long computation time to react to unexpected events. To reduce response time, we suggest three techniques for accelerating rule comparison. We test these techniques as well as other operational policies that can be used in the SBRTS method through computational experiments on a number of test problems.

A Simulation Framework for the Performance Assessment of Shop-Floor Control Systems

The authors discuss the concept and design criteria for a framework that facilitates the performance assessment of shop-floor control systems. Their basic concept includes a simulation model that emulates the shop floor of a wafer fab, sends information to the control system, and receives information back from the control system. The shop-floor control system is realized as a separate module that interfaces to the simulator via a data layer that contains the current shop-floor status and the control information generated by the controller. The authors provide detailed information on how the simulation model and shop-floor control system communicate and how each system triggers events in the other system. They show how this framework supports the performance assessment of the shop-floor control system under consideration. They also present a prototype of the framework currently implemented in the course of the SRC/International Sematech FORCe project “Scheduling of Semiconductor Wafer Fabrication Facilities.”

Design-tool for Rapid Thermal Processors for Optimal Trajectory Tracking

It has become an irreversible trend in recent years that the semiconductor wafer fabrication requires shorter processing time, greater flexibility and lower capital cost. Rapid thermal processing (RTP) has demonstrated its potential to meet such requirements while becoming a key process for manufacturing advanced semiconductor devices. Ever decreasing feature sizes require extremely tightly controlled processing conditions, especially the temperature trajectory to be precisely followed across the wafer. This paper presents a systematic methodology for RTP chamber design, based on the 3-dimensional physics-based model of a generic RTP chamber. After experimentally validated, the physics-based model is reduced to a lower-order model without sacrificing its fidelity for computational efficiency. With a reduced-order model, optimization studies are performed to determine how small the deviation of the wafer temperature from the pre-specified trajectory can be made in a given design. The results of the optimization studies indicate the goodness of the given RTP design, unravel clues for design improvements, and may provide guidelines for control implementation.

Cycle time management during production ramp-up

Aggressive capacity ramp rate of a semiconductor wafer fabrication is vital for the commercial success of the enterprise. Basic requirements are short and stable production cycle times to timely qualify equipment and to provide acceptable yield. Therefore, in the ramp-up environment which is characterized by high variability and uncertainty, an adequate methodology is required to properly manage the conflict of short cycle times and fast throughput increase. This paper presents a methodology to manage cycle time by closely monitoring and limiting the work in process (WIP), by means of the so-called “WIP caps”. Used consequently, this methodology allows the ramp rate to accelerate as soon as the factory performance enables this while keeping cycle times under control.

Selection of dispatching rules on multiple dispatching decision points in real-time scheduling of a semiconductor wafer fabrication system

Semiconductor wafer fabrication involves one of the most complex manufacturing processes ever used. To control such complex systems, it is a challenge to determine appropriate dispatching strategies under various system conditions. Dispatching strategies are classified into two categories: a vehicle-initiated dispatching policy and a machine-initiated dispatching policy. Both policies are important to improve the system performance, especially for the real time control of the system. However, there has been little research focusing on combining them under various situations for the semiconductor manufacturing system. In addition, it is shown that no single dispatching strategy consistently dominates others in all situations. Therefore, the goal of this study is to develop a scheduler for selection of dispatching rules for dispatching decision variables in order to obtain the desired performance measures given by a user for each production interval. For the proposed methodology, simulation and competitive neural network approaches are used. The results of the study indicate that applying our methodology to obtaining a dispatching strategy is an effective method considering the complexity of semiconductor wafer fabrication systems.

Development of a real-time multi-objective scheduler for a semiconductor fabrication system

Semiconductor wafer fabrication involves possibly one of the most complex manufacturing processes ever used. This causes a number of decision problems. A successful system control strategy would assign appropriate decision rules for decision variables. Therefore, the goal of this study is to develop a scheduler for the selection of decision rules for decision variables in order to obtain the desired performance measures given by a user at the end of a certain production interval. In this proposed methodology, a system control strategy based on a simulation technique and a competitive neural network is suggested. A simulation experiment was conducted to collect the data containing the relationship between the change of decision rule set and current system status and the performance measures in the dynamic nature of semiconductor manufacturing fabrication. Then, a competitive neural network was applied to obtain the scheduling knowledge from the collected data. The results of the study indicate that applying this methodology to obtaining a control strategy is an effective method considering the complexity of semiconductor wafer fabrication systems.

Investigation of flow mechanisms in semiconductor wafer fabrication

The semiconductor wafer fabrication manufacturing environment is one of the most difficult in which to plan and control. Long and re-entrant routings and high yield loss on new products are two characteristics that impact system performance. This research provides an exploratory investigation of two simplified flow control mechanisms to determine if they might offer promise for further research in this complex environment. Most scheduling and control systems are data intensive and require real-time feedback. Our research explores the use of simple, limited data, flow control mechanisms. The results indicate that these newer planning and control mechanisms, which offer a systems perspective, perform well when compared with a real time, data-intensive, flow control mechanism.

Translating overall production goals into distributed flow control parameters for semiconductor manufacturing

As manufacturing systems are often operated under distributed control, translating overall production goals, such as system output rate and cycle time, into local flow control targets for internal operations, such as work-in-process (WIP) levels and part release intervals, has been a significant and challenging research topic. This paper studies the problem for semiconductor wafer fabrication plants, where there are multiple part types, failure-prone machines, and deterministic reentrant process flows. Such a system is first modeled as a failure-free and reentrant open queuing network with an aggregated part type. By exploiting a decomposition-based approximation, a backward queuing network analysis (BQNA) is designed to derive flow control parameters in terms of means and variations of input processes for each machine group. These derived control parameters can be utilized to obtain managerially tangible requirements for cycle times and WIP levels and to create guidelines for distributed flow control leading to the desired overall production goals. Comparisons with simulation results for two example wafer fabrication models demonstrate the accuracy and computational efficiency of BQNA and its potential for real applications.

Modelling and analysis of wafer fabrication scheduling via generalized stochastic Petri net and simulated annealing

Some of the important characteristics of the semiconductor wafer fabrication factories are re-entrant process flows, a dynamic and uncertain environment, stringent production control requirements, etc. that pose a major challenge to the scheduling decisions in integrated circuit wafer fabrication process. Keeping in view the high capital investment and quick response to the market changes, it is essential for the integrated circuit fabrication process to exercise effective control on its production operations so that production resources can be employed in a flexible and efficient manner. The present research has focussed on the development of a generalized stochastic Petri net model that faithfully captures dynamic behaviours such as re-entrant processing, machine failures, loading and unloading, etc., pertaining to wafer fabrication. A simulated annealing-based scheduling strategy using mean cycle time and tardiness as performance measures was also developed to obtain an efficient and robust schedule for a known hard problem. Analysis of variance was applied to examine the interaction effects of various scheduling rules and to identify the main as well as the interaction effects of dispatching rules, dispatching rules and set-up rules, and set-up rules and batching rules. Paired t-tests were applied to assess the performance of rule combinations for lot and batch scheduling. The proposed simulated annealing-based solution methodology was tested on a well-known data set adopted from the literature and its performance reveals that simulated annealing-based scheduling rules work better than existing rules in terms of the two performance measures mean cycle time and tardiness.

Scheduling complex job shops using disjunctive graphs: A cycle elimination procedure

Wafer fabrication is the most complex phase in the semiconductor manufacturing process. Semiconductor wafer fabrication facilities (wafer fabs) contain re-entrant product flow through machines operating in parallel. Some of these machines incur sequence-dependent set-ups, while others are capable of processing multiple jobs in batches. This complex job shop can be modelled as a disjunctive graph, and then scheduled using a modified Shifting Bottleneck heuristic. The existence of the batch-processing machines in the complex job shop creates the potential for cyclic schedules to be produced by the modified Shifting Bottleneck approach, primarily due to the existence of dummy batching nodes and delayed precedence constraints. We propose a cycle elimination procedure to assist in maintaining schedule feasibility during the modified Shifting Bottleneck procedure.

D-Optimal Sequential Experiments for Generating a Simulation-Based Cycle Time-Throughput Curve

A cycle time-throughput curve quantifies the relationship of average cycle time to throughput rates in a manufacturing system. Moreover, it indicates the asymptotic capacity of a system. Such a curve is used to characterize system performance over a range of start rates. Simulation is a fundamental method for generating such curves since simulation can handle the complexity of real systems with acceptable precision and accuracy. A simulation-based cycle time-throughput curve requires a large amount of simulation output data; the precision and accuracy of a simulated curve may be poor if there is insufficient simulation data. To overcome these problems, sequential simulation experiments based on a nonlinear D-optimal design are suggested. Using the nonlinear shape of the curve, such a design pinpoints p starting design points, and then sequentially ranks the remaining n – p candidate design points, where n is the total number of possible design points being considered. A model of a semiconductor wafer fabrication facility is used to validate the approach. The sequences of experimental runs generated can be used as references for simulation experimenters.

Offshore investors place their chips on Chinese foundries

Judging China an electronics superpower in the making, large corporations like Japan's NEC, as well as independent Taiwanese investors, are racing to set up semiconductor wafer fabrication lines within its territory. This paper examines how, all the same, given the overall downturn in the chip sector, some observers wonder whether this is the right time for companies to start building expensive fabs in China.

Using in-line equipment condition and yield information for maintenance scheduling and dispatching in semiconductor wafer fabs

Yield is one of the most important measures of manufacturing performance in the semiconductor industry, and equipment condition plays a critical role in determining yield. Researchers and practitioners alike have traditionally treated the problems of equipment maintenance scheduling and production dispatching independently, ignoring how equipment condition may affect different product types or families in different ways. This paper addresses the problem of how to schedule maintenance and production for a multiple-product, multiple-stage production system. The problem is based on the situation found in semiconductor wafer fabrication where the equipment condition deteriorates over time, and this condition affects the yield of the production process. We extend a recently developed Markov decision process model of a single-stage system to account for the fact that semiconductor wafers have multiple layers and thus make repeated visits to each workstation. We then propose a methodology by which the single-stage results can be applied in a multi-stage system. Using a simulation model of a four-station wafer fab, we test the policies generated by the model against a variety of other maintenance and dispatching policy combinations. The results indicate that our method provides substantial improvements over traditional methods and performs better as the diversity of the product set increases. In the scenarios examined, the reward earned using the policies from the combined production and maintenance scheduling method was an average of more than 70° higher than the reward earned using other policy combinations such as a fixed-state maintenance policy and a first-come, first-serve dispatching policy.

Shift scheduling for steppers in the semiconductor wafer fabrication process

In this paper, an approach is proposed for scheduling stepper machines that are acting as bottleneck machines in the semiconductor wafer fabrication process. We consider the problem of scheduling the steppers for an 8 hour shift, determining which types of wafer lots to work on each machine. The scheduling objective is to find the optimal stepper allocations such that the schedule meets target production quantities that have been derived from the given target Work-In-Process (WIP) levels. A Mixed Integer Programming (MIP) model is formulated, and three heuristic approaches are proposed and tested to approximately solve the M1P model. Numerical tests show that one of the proposed heuristics using linear programming relaxation of MIP generates, on average, schedules within 5° of the optimum values.

Using in-line equipment condition and yield information for maintenance scheduling and dispatching in semiconductor wafer fabs

Yield is one of the most important measures of manufacturing performance in the semiconductor industry, and equipment condition plays a critical role in determining yield. Researchers and practitioners alike have traditionally treated the problems of equipment maintenance scheduling and production dispatching independently, ignoring how equipment condition may affect different product types or families in different ways. This paper addresses the problem of how to schedule maintenance and production for a multiple-product, multiple-stage production system. The problem is based on the situation found in semiconductor wafer fabrication where the equipment condition deteriorates over time, and this condition affects the yield of the production process. We extend a recently developed Markov decision process model of a single-stage system to account for the fact that semiconductor wafers have multiple layers and thus make repeated visits to each workstation. We then propose a methodology by which the single-stage results can be applied in a multi-stage system. Using a simulation model of a four-station wafer fab, we test the policies generated by the model against a variety of other maintenance and dispatching policy combinations. The results indicate that our method provides substantial improvements over traditional methods and performs better as the diversity of the product set increases. In the scenarios examined, the reward earned using the policies from the combined production and maintenance scheduling method was an average of more than 70% higher than the reward earned using other policy combinations such as a fixed-state maintenance policy and a first-come, first-serve dispatching policy.

Performance evaluation of re-entrant lines with multi-class jobs and multi-server workstations

An approximation method is proposed for estimating the performance measures of re-entrant lines with multiserver workstations based on the Mean Value Analysis (MVA) technique. The system of interest can be found in the semiconductor wafer fabrication line in which several circuit types are manufactured through re-entrant processes at both the single-job and the batch workstations. Each workstation may have several identical machines. Multi-class jobs are assumed to be processed in a predetermined routing, in which some processes may utilize the same workstation several times in the re-entrant fashion. The performance measures of interest are the steady-state average of the cycle time of each job class, the queue length of each buffer, and the throughput of the system. The system may not be modelled by a product form queueing network due to the inclusion of batch machines, multi-class jobs with different processing times, and multi-server workstations. Thus, a methodology is proposed for analysing such a reentrant line approximately using the iterative procedures based upon the MVA and some heuristic adjustments. Results of numerical tests are provided to show the performance of the proposed approach against the simulation results.

Shift scheduling for steppers in the semiconductor wafer fabrication process

In this paper, an approach is proposed for scheduling stepper machines that are acting as bottleneck machines in the semiconductor wafer fabrication process. We consider the problem of scheduling the steppers for an 8 hour shift, determining which types of wafer lots to work on each machine. The scheduling objective is to find the optimal stepper allocations such that the schedule meets target production quantities that have been derived from the given target Work-In-Process (WIP) levels. A Mixed Integer Programming (MIP) model is formulated, and three heuristic approaches are proposed and tested to approximately solve the MIP model. Numerical tests show that one of the proposed heuristics using linear programming relaxation of MIP generates, on average, schedules within 5% of the optimum values.

A modified shifting bottleneck heuristic for minimizing total weighted tardiness in complex job shops

Increases in the demand for integrated circuits have highlighted the importance of meeting customer quality and on-time delivery expectations in the semiconductor industry. A modified shifting bottleneck heuristic is developed for minimizing the total weighted tardiness in a semiconductor wafer fabrication facility. This ‘complex’ job shop is characterized by re-entrant or re-circulating product flow through a number of different tool groups (one or more machines operating in parallel). These tool groups typically contain batching machines, as well as machines that are subject to sequence-dependent setups. The disjunctive graph of the complex job shop is presented, along with a description of the proposed heuristic. Preliminary results indicate the heuristic's potential for promoting on-time deliveries by semiconductor manufacturers for their customers' orders. Copyright © 2002 John Wiley & Sons, Ltd.

A generalized Petri net modeling approach for the control of re-entrant flow semiconductor wafer fabrication

Re-entrant flow manufacturing lines, such as occur in semiconductor wafer fabrication, are characterized by a product routing that consists of multiple visits to a workstation or group of workstations during the manufacturing process. In this paper, a modeling approach is based on the use of generalized Petri nets for a re-entrant flow manufacturing line is presented. Specifically, three Petri net models representing a re-entrant flow line with three work centers and six machines are modeled. How these models may be used to represent a variety of queuing disciplines and work release policies is discussed.