Semiconductor Manufacturing Process Research Articles

Sparse deep encoded features with enhanced sinogramic red deer optimization for fault inspection in wafer maps

AbstractDue to the complexity and dynamics of the semiconductor manufacturing processes, wafer bin maps (WBM) present various defect patterns caused by various process faults. The defect type detection on wafer maps provides information about the process and equipment in which the defect occurred. Recently, automatic inspection has played a vital role in meeting the high-throughput demand, especially with deep convolutional neural networks (DCNN) which shows promising efficiency. At the same time, the need for a large amount of labeled and balanced datasets limits the performance of such approaches. In addition, complex DCNN in recognition tasks can provide redundant features that cause overfitting and reduce interpretability. In this paper, a new hybrid deep model for wafer map fault detection to get over these challenges is proposed. Firstly, a new convolutional autoencoder (CAE) is employed as a synthetization model to fix the high imbalance problem of the dataset. Secondly, for efficient dimensionality reduction, an embedding procedure is applied to the synthesized maps to get sparse encoded wafer maps by reinforcing a sparsity regularization in an encoder-decoder network to form a sparsity-boosted autoencoder (SBAE). The sparse embedding of wafer maps guarantees more discriminative features with 50% reduction in spatial size compared to the original wafer maps. Then, the 2D encoded sparse maps are converted to 1D sinograms to be fed later into another aggressive feature reduction stage using a new modified red deer algorithm with a new tinkering strategy. The resultant feature pool is reduced to ~ 25 1D feature bases, i.e., ~ 1.5% of the initial size of the 2D wafer maps. Finally, for the prediction stage, a simple 1DCNN model is introduced. The proposed inspection model is tested via different experiments on real-world wafer map dataset (WM-811K). Compared to state-of-the-art techniques, the proposed model outperforms their performance even with small-sized 1D feature pool. The average testing accuracy are 98.77% and 98.8% for 9 and 8 types of faults, respectively.

Influences and Diffusion Effects of Lithium Contamination during the Thermal Oxidation Process of Silicon

Due to the increasing number of application fields using lithium compounds in the microelectronics sector, it is necessary to investigate the contamination influence and the effects of lithium on silicon and silicon oxide. To be able to use lithium in a controlled manner in complementary metal–oxide–semiconductor clean room environments, the various diffusion effects during an important process in semiconductor manufacturing, the thermal oxidation of silicon to form silicon oxide, are investigated herein. This includes the diffusion within the wafer, between wafers, and into the furnace environment. For this purpose, wafers are intentionally contaminated, oxidized, and then analyzed with vapor phase decomposition inductively coupled plasma mass spectrometry. The results of this study are correlated with typical contamination levels in state‐of‐the‐art cleanroom facilities to enable classifications of the results for the semiconductor sector. Furthermore, the effect on the growth rate and uniformity of silicon oxide is evaluated by ellipsometry and topography measurements. Finally, electrical measurements of the oxide layer have shown that there is a significant influence on the silicon oxide quality, meaning that lithium can have a detrimental effect on devices.

Wire Bow In Situ Measurement for Monitoring the Evolution of Sawing Capability of Diamond Wire Saw during Slicing Sapphire.

Electroplated diamond wire sawing is widely used as a processing method to cut hard and brittle difficult-to-machine materials. Currently, obtaining the sawing capability of diamond wire saw through the wire bow is still difficult. In this paper, a method for calculating the sawing capability of diamond wire saw in real-time based on the wire bow is proposed. The influence of the renewed length per round trip, crystal orientation of sapphire, wire speed, and feed rate on the wire sawing capability has been revealed via slicing experiments. The results indicate that renewing the diamond wire saw, and reducing the wire speed and feed rate can delay the reduction in sawing capability. Furthermore, controlling the value of renewed length per round trip can make the diamond wire saw enter a stable cutting state, in which the capability of the wire saw no longer decreases. The sawing capability of diamond wire saw cutting in the A-plane of the sapphire is smaller than that of the C-plane, and a suitable feed rate or wire speed within the range of sawing parameters studied in this study can avoid a rapid decrease in the sawing capability of the wire saw during the cutting process. The knowledge obtained in this study provides a theoretical basis for monitoring the performance of the wire saw, and guidance for the wire cutting process in semiconductor manufacturing. In the future, it may even be possible to provide real-time performance parameters of diamond wire saw for the digital twin model of wire sawing.

Deep ensemble learning for material removal rate prediction in chemical mechanical planarization with pad surface topography

Chemical mechanical planarization (CMP) stands as a critical process in semiconductor manufacturing, necessitating precise prediction of material removal rate (MRR) to achieve optimal global planarization of material surface step heights. A notable hurdle in MRR prediction lies in the nonlinear pad-wafer interaction stemming from variations in the polishing pad surface. Despite numerous extant studies examining the asperity of the pad surface and the wafer-pad contact, aspects such as slurry lubrication and micro-topographical structure of the pad surface remain unaddressed. This study firstly proposes a deep ensemble learning-based approach for MRR prediction, leveraging the intricate interactions between the overall features of the pad surface and the polishing pressure. We experimentally generated diverse pad surfaces by controlling the process variables governing pad surface topography. The Multi-TabNet model, constructed by independently training multiple TabNet instances with distinct initialization and hyperparameters, furnishes a framework for MRR prediction across a broad spectrum of pad surface features, encompassing pores and cores. The results demonstrate a root mean square error of 80 Å/min, with the error margin reduced by up to 70 % compared to predictions utilizing a single parameter of the pad surface. Furthermore, it exhibits an error improvement exceeding 17 % relative to the existing method solely considering asperity. This study not only imparts insights for addressing MRR variations contingent on pad condition but also facilitates dependable material removal even on variable pad surfaces due to conditioner wear.

An adaptive Bayesian approach for improved sensitivity in joint monitoring of mean and variance using Max-EWMA control chart

This article introduces an adaptive approach within the Bayesian Max-EWMA control chart framework. Various Bayesian loss functions were used to jointly monitor process deviations from the mean and variance of normally distributed processes. Our study proposes the mechanism of using a function-based adaptive method that picks self-adjusting weights incorporated in Bayesian Max-EWMA for the estimation of mean and variance. This adaptive mechanism significantly enhances the effectiveness and sensitivity of the Max-EWMA chart in detecting process shifts in both the mean and dispersion. The Monte Carlo simulation technique was used to calculate the run-length profiles of different combinations. A comparative performance analysis with an existing chart demonstrates its effectiveness. A practical example from the hard-bake process in semiconductor manufacturing is presented for practical context and illustration of the chart settings and performance. The empirical results showcase the superior performance of the Adaptive Bayesian Max-EWMA control chart in identifying out-of-control signals. The chart’s ability to jointly monitor the mean and variance of a process, its adaptive nature, and its Bayesian framework make it a useful and effective control chart.

Overlay Mark Design Using Irregular Grating Patterns

Overlay refers to controlling the vertical alignment and misalignment between circuit patterns manufactured in the previous process and circuit patterns manufactured in the current process during the stacking process of circuit patterns in the semiconductor manufacturing process. A critical factor in ensuring precise overlay measurements is using an optimized overlay mark design. Many semiconductor manufacturers have put considerable effort into optimizing overlay measurement marks to reduce high costs. However, image-based overlay measurement encounters several challenges, including resolution degradation, image distortion, and noise introduction during digital data conversion. These issues can amplify the uncertainty of overlay measurements, impair optical resolution, and heighten the risk of mismeasurement. In this paper, we introduce irregular grating patterns designed to address the principal challenges faced by the commonly utilized Advanced Imaging Metrology (AIM) marks, namely large overlays and image distortion. Furthermore, we propose an overlay mark capable of precisely identifying overlays exceeding half a pitch and incorporating as much data as possible within the limits of optical resolution. This aims to improve overlay measurement performance. The experimental findings demonstrate that the proposed Pulsated Grating Target (PGT) mark enhances overall measurement uncertainty by approximately 17% compared to the AIM mark. The practical applicability of the PGT was validated through experiments, and we achieved enhanced precision and reliability in overlay measurements by resolving the issue of large overlays—the most significant challenge with grating patterns—and simultaneously enhancing mark performance.

Recovery and reuse of magnetic silica-coated iron oxide particles for eco-friendly chemical mechanical planarization

Chemical mechanical planarization (CMP), a crucial process in semiconductor manufacturing, raises environmental concerns due to increased waste generation, prompting questions about its long-term sustainability. To address this issue, we explore an innovative approach to the waste management and recycling process by introducing magnetite (Fe3O4) particles coated with SiO2 layers, aimed at enhancing the CMP recycling efficiency. These core-shell particles exhibit controlled shell thickness, and modified surface charges, as confirmed by various analytical techniques. Our results reveal that slurries containing Fe3O4@SiO2 particles significantly improve W removal rates and surface smoothness compared to conventional slurries, attributed to the optimal mechanical properties. Moreover, the magnetite core facilitates the magnetic separation and recovery of used particles from spent slurries, offering a cost-effective and environmentally friendly solution. The recycling efficacy of these particles is demonstrated through multiple CMP cycles, showing consistent removal rates and surface quality, highlighting the potential of magnetic separation in sustainable CMP.

Correlation analysis of sampled wafer profile maps based on a deep reconstruction model

In the semiconductor manufacturing process, various kinds of metrology and test data can form different types of wafer maps. By analyzing the correlation of multiple types of wafer maps, especially for the wafer bin maps (WBMs) and the wafer profile maps, the faulty inline manufacturing steps strongly correlated with end-of-line yield can be found for yield improvement. This paper proposes a correlation analysis method based on a deep reconstruction model to integrate the knowledge among multiple types of wafer maps for root cause analysis. First, the sparsely sampled wafer profile maps are restored to original wafer profile maps through the deep reconstruction model for obtaining more information. And then, the correlation between the WBMs and the reconstructed profile maps is calculated. The process step whose wafer profile maps have the highest correlation with WBMs is highly related to the fault. Experiments on the real-world dataset demonstrate that the proposed method can restore the wafer profile map well and has high accuracy in matching the relevant process wafer profile map based on the WBMs.

Robust Control Chart Application in Semiconductor Manufacturing Process

Statistical Process Control (SPC) charts are frequently used in the semiconductor manufacturing environment to monitor process quality and detect special-cause variations, hence, to take corrective actions when necessary. The important aspects of control charts to consider on production floors are identifying the primary objective of implementing control charts, the type of data to monitor and the most appropriate control limits to establish. When the quality data is a type of attribute data like the proportion of defectives from a production lot, a p-chart approach is most suitable. In p-chart applications, although the assumption of normally distributed process data is not mandatory, the widespread practice is to assume the normal distribution of process data when establishing the control limits. Yet again, the reality of industrial settings is that process data are most likely influenced by outliers, resulting in highly skewed distributions. This paper addresses these issues by proposing robust SPC charting techniques to detect special-cause variations in the semiconductor manufacturing processes. Here, we present a case study of a semiconductor company in Malaysia, Dominant Opto Technologies Sdn. Bhd. to propose three robust statistical approaches for monitoring the proportion of defectives in production lots. We apply M-estimates, median, and interquartile range to calculate the upper control limits (UCL) and found that robust estimators are more effective in detecting early process deterioration and capturing the out-of-control (OOC) conditions better than traditional control charts. By proposing robust methods, this study enlightens the practical aspects of process quality improvement for real-life manufacturing setups. Because a high OOC rate may impact manufacturing productivity, we recommend the decision-makers choose the types of control charts based on the implications of each robust approach toward quality and productivity. The significance of this study includes providing insights into setting up the appropriate attribute control charts for detecting defective proportions for professionals and SPC researchers working in these areas.

Modified Levey-Jennings Chart with Robust Estimator: A Case of Semiconductor Manufacturing Process

In the era of Industrial Revolution 4.0 and smart manufacturing, the development and deployment of control charts used in the semiconductor industry need to be automated. Consequently, artificial intelligence-based automation methods typically encompass the deployment of statistical software such as JMP. Automation involves frequent dataset updates; the control limits are recalculated as the parameters change (non-stationary behaviour). This requires the user to define the control chart type before its deployment on the production floor. An initially normally distributed dataset may be skewed during the process owing to the influence of outliers. If a user selects a chart based on normality assumptions, detecting a process-mean shift may be impossible if the recalculated limit fluctuates. In the semiconductor industry, a process-mean shift occurs owing to special cause variations in the process. This signals process deterioration, which may affect the quality of the product. It is unknown when outliers will affect the equilibrium of normality assumptions; therefore, it is important to develop an automated, robust control chart that can detect special cause variations under non-stationary conditions. This study proposes the use of Huber’s M-estimators in the Levey-Jennings chart to detect special cause variations in a semiconductor manufacturing process. This study computes the robust M-estimates of all available samples to calculate the new limits in the Levey-Jennings chart. This new chart is referred to as the modified Levey-Jennings with a robust Huber M-estimator (MLVHM). Using production data from Dominant Opto Technologies Sdn. Bhd., Malaysia, a statistical comparison of the MLVHM and Levey-Jennings charts was performed. While the MLVHM is stable, the absolute difference in dispersion between the two charts ranges between 25.26% and 47.91% owing to standard deviation variation in the Levey-Jennings chart in non-stationary situations with outliers. The study concludes that the MLVHM chart is robust and suitable for industrial automatic flow applications.

Smart Circuit Design Machine Learning-Driven Optimization for Enhanced Performance in Electronics and Computer Engineering.

In the realm of Electronics and Computer engineering, achieving optimal performance of circuits amidst escalating complexity poses significant challenges. Traditional manual optimization techniques are often inadequate to navigate the intricacies of modern electronic systems. This paper advocates for the adoption of machine learning-driven optimization as a transformative approach to smart circuit design. By leveraging machine learning algorithms, engineers can systematically explore the expansive design space, discern complex relationships between circuit parameters and performance metrics, and ultimately enhance the efficiency and effectiveness of electronic circuits. This paper comprehensively reviews the application of machine learning techniques in circuit design optimization. Supervised learning algorithms such as neural networks, support vector machines, and decision trees enable the modeling of intricate interdependencies within electronic circuits. Unsupervised learning techniques, including clustering and dimensionality reduction, facilitate efficient exploration of the design landscape by identifying patterns and correlations. Additionally, reinforcement learning algorithms offer an autonomous approach to circuit optimization through iterative learning and refinement. Real-world applications of machine learning-driven optimization in electronics and computer engineering span various domains, including power-efficient integrated circuits, signal processing algorithm optimization, and layout optimization for enhanced performance and reliability. Moreover, machine learning techniques play a crucial role in mitigating variability in semiconductor manufacturing processes, ensuring robustness and reliability of electronic systems in the face of uncertainties. Despite the promising potential of machine learning in circuit design optimization, challenges such as dataset acquisition, model interpretability, and scalability to complex circuits persist. Addressing these challenges requires innovative research endeavors, including the development of hybrid optimization techniques and novel hardware architectures. DOI: https://doi.org/10.52783/tjjpt.v45.i02.6339

Nanoimprint-induced strain engineering of two-dimensional materials

The high stretchability of two-dimensional (2D) materials has facilitated the possibility of using external strain to manipulate their properties. Hence, strain engineering has emerged as a promising technique for tailoring the performance of 2D materials by controlling the applied elastic strain field. Although various types of strain engineering methods have been proposed, deterministic and controllable generation of the strain in 2D materials remains a challenging task. Here, we report a nanoimprint-induced strain engineering (NISE) strategy for introducing controllable periodic strain profiles on 2D materials. A three-dimensional (3D) tunable strain is generated in a molybdenum disulfide (MoS2) sheet by pressing and conforming to the topography of an imprint mold. Different strain profiles generated in MoS2 are demonstrated and verified by Raman and photoluminescence (PL) spectroscopy. The strain modulation capability of NISE is investigated by changing the imprint pressure and the patterns of the imprint molds, which enables precise control of the strain magnitudes and distributions in MoS2. Furthermore, a finite element model is developed to simulate the NISE process and reveal the straining behavior of MoS2. This deterministic and effective strain engineering technique can be easily extended to other materials and is also compatible with common semiconductor fabrication processes; therefore, it provides prospects for advances in broad nanoelectronic and optoelectronic devices.

Effects of cutting conditions on materials properties of austenitic stainless steels

Austenitic stainless steel SUS304 is widely used in various engineering applications, including semiconductor manufacturing equipment and food processing machinery, owing to its exceptional material characteristics such as non-magnetic properties, high corrosion resistance, strength, and ductility. However, concerns have arisen in recent years regarding potential alterations in the material properties of austenitic stainless steel after machining processes. As the cutting process was conducted widely to make various engineering applications with different machining conditions, an examination of the effect of machining conditions on the material properties is important. In the present study, the influence of cutting conditions on the microstructure and mechanical of SUS304 was experimentally and numerically investigated, where three types of ball-end mills with rake angles (- 20°, − 3°, and 5°) and different cutting speeds (50 m･min−1 and 100 m･min−1) were conducted with plane and side machining to investigate the cutting properties. Material properties of SUS304 can be changed by the cutting resistance of the above cutting process, in particular the low rake angles under plane machining, where the high cutting resistance makes high dislocation density and strain-induced martensite formation. This occurrence made the low corrosion resistance as well as low ductility. On the contrary, no significant effect of the cutting speeds on the cutting resistance was detected compared to the condition of the rake angle on the plane machining. The reasons behind this will be discussed in detail systematically in this paper. From this approach, it could be clarified to maintain the high material properties of SUS304 even after the cutting process, which could be useful to make design of the engineering applications.

Universal Deoxidation of Semiconductor Substrates Assisted by Machine Learning and Real-Time Feedback Control.

Substrate oxidation is inevitable when exposed to ambient atmosphere during semiconductor manufacturing, which is detrimental to the fabrication of state-of-the-art devices. Optimizing the deoxidation process in molecular beam epitaxy (MBE) for random substrates poses a multidimensional challenge and is sometimes controversial. Due to variations in substrates and growth processes, the determination of the deoxidation condition heavily relies on the individual's expertise, yielding inconsistent results. This study employs a machine learning model that integrates interpolation and vision transformer (Interpolation-ViT) techniques. The model utilizes reflection high-energy electron diffraction videos as input to predict the status of the substrate, enabling automated deoxidation within a controlled architecture for various substrates. Furthermore, we highlight the potential of models trained on data from specific MBE equipment to achieve high-accuracy deployment on different pieces of equipment. In contrast to traditional methods, our approach holds exceptional value, as it standardizes deoxidation temperatures across diverse equipment and substrates. This significantly advances the standardization of the semiconductor process. The concepts and methods presented are expected to revolutionize semiconductor manufacturing processes in the optoelectronic and microelectronic industries.

Microstructural characterization and inductively coupled plasma-reactive ion etching resistance of Y2O3–Y4Al2O9 composite under CF4/Ar/O2 mixed gas conditions

In the semiconductor manufacturing process, when conducting inductively coupled plasma-reactive ion etching in challenging environments, both wafers and the ceramic components comprising the chamber’s interior can be influenced by plasma attack. When ceramic components are exposed to long-term plasma environments, the eroded components must be replaced. Furthermore, non-volatile reactants can form and settle on semiconductor chips, acting as contaminants and reducing semiconductor production yield. Therefore, for semiconductor processing equipment parts to be utilized, it is necessary that they exhibit minimized generation of contaminant particles and not deviate significantly from the composition of conventionally used Al2O3 and Y2O3; part must also last long in various physicochemical etching environment. Herein, we investigate the plasma etching behavior of Y2O3–Y4Al2O9 (YAM) composites with a variety of mixing ratios under different gas fraction conditions. The investigation revealed that the etching rates and changes in surface roughness for these materials were significantly less than those of Y2O3 materials subjected to both chemical and physical etching. Microstructure analysis was conducted to demonstrate the minimization of crater formation. Mechanical properties of the composite were also analyzed. The results show that the composite can be commercialized as next-generation ceramic component in semiconductor processing equipment applications.

Quantum interference in a high-transition-temperature superconductor based on nanoslits on SrTiO3 substrate

The Josephson junction, a key component of superconducting quantum circuits, is much less mature, especially for the high-transition (high-Tc) temperature cuprate superconductors. Herein, we report on the realization of high-Tc Josephson junction based on nanoslits on a SrTiO3 substrate. We demonstrate the ability to manipulate the current–voltage characteristics of YBa2Cu3O7−x bridges continuously from superconducting current-dominated to Josephson junction behavior by changing the irradiation parameters of the focused Ga+ ion beam on a single-crystal SrTiO3 substrate. The periodic critical current that depends on the magnetic flux coupled into the superconducting quantum interference devices was observed, which exactly reflects the effects of quantum tunneling and flux quantization. To some extent, this weak link within the framework of the semiconductor manufacturing process shows the potential to provide a cost-effective, highly efficient, and reliable pathway for scaling up quantum mechanical superconducting circuits, which is promising for the fabrication process.

Run-indexed time-varying Bayesian optimization with positional encoding for auto-tuning of controllers: Application to a plasma-assisted deposition process with run-to-run drifts

Bayesian optimization (BO) has emerged as a useful paradigm for automatic calibration (aka auto-tuning) of advanced optimization- and learning-based controllers whose closed-loop performance depends on the choice of several tuning parameters in highly nonlinear and nonconvex ways. However, BO approaches to controller auto-tuning commonly rely on the assumption that system dynamics remain constant, which does not hold for systems with time-varying dynamics, for example, due to gradual aging or persistent environmental drifts. This challenge can be further compounded when gradual and persistent system drifts occur over a series of process runs. Existing time-varying BO (TVBO) approaches with spatio-temporal kernels fall short of effectively handling an integer run index, which is imperative for capturing run-to-run changes in the system behavior. To this end, this paper presents a run-indexed TVBO (RI-TVBO) approach that can systematically account for run-to-run process drifts as the system is queried over sequential process runs. The proposed approach relies on adapting the non-stationary Wiener process kernel to accommodate an integer run index, instead of time. This is done via positional encoding that incorporates the integer run index and, thus, enables describing run-to-run variations in system dynamics. The positional embedding vector associated with each run index is then mapped onto a scalar value to leverage the relationships between different process runs within the probabilistic surrogate model of the objective function in RI-TVBO. The performance of RI-TVBO is evaluated for auto-tuning of an offset-free model predictive controller for a low-temperature plasma-assisted process for thin film deposition. Simulation results demonstrate the superior performance of RI-TVBO over standard BO and TVBO under different scenarios of run-to-run process drifts encountered in plasma-assisted deposition processes in semiconductor manufacturing.

Understanding the contributions of F–, HF, and HF2– to the etching of SiO2 and unveiling the reaction kinetics to represent etching behavior of SiO2 up to pH 5

Understanding of the silicon dioxide (SiO2) etching mechanism in hydrofluoric acid (HF) solutions is important in semiconductor manufacturing processes. A study on the previous SiO2 etching mechanism claimed that only difluoride (HF2–) participated in SiO2 etching. However, in this study, it was observed that the etching of SiO2 occurred in the HF solution, where difluoride barely existed. Hence, a new SiO2 etching mechanism and reaction rate were proposed. Various concentrations of HF and ammonium fluoride (NH4F) under varying pH conditions were used to etch SiO2, leading to an SiO2 etching rate of 510[F–] + 610[HF] + 2890[HF2–] (Å/min). HF2– was the primary contributor to SiO2 etching; however, unlike the previous SiO2 etching mechanism, the effects of F– and HF on the etching of SiO2 were included in the rate of SiO2 etching. The SiO2 etching rate, considering the reactions between various fluorine species with varying SiO2 surface states, effectively represented the SiO2 etching behavior under various conditions over a broader pH range, up to pH 5. Controlling the ratio of the fluorine species, F–, HF, and HF2–, our etching model could also be extended to the selective etching of SiO2.

Modified electronic structure of amorphous Mn‐Si‐Te for OTS application: Improved thermal stability by the formation of Mn‐Te bonding

A critical element within the 3D Xpoint architecture is the Ovonic threshold switch (OTS) material, which serves a crucial role as a selector. The development of novel OTS materials devoid of hazardous elements such as As and Se is imperative for mitigating environmental impact. The Si‐Te binary telluride is a representative As/Se‐free OTS material, demonstrating stable switching. However, its thermal stability is insufficient for enduring annealing processes in semiconductor manufacturing. To address this challenge, this study proposes the incorporation of Mn into the Si‐Te alloy. While the introduction of transition metals into chalcogenide glass typically reduces the electrical resistivity, potentially compromising the ON/OFF ratio, the off current for the device containing 26 at.% Mn is observed to be lower than that for the undoped Si‐Te device. Furthermore, the thermal stability of the Mn‐Si‐Te film surpasses that of its pristine counterpart. X‐ray photoelectron spectroscopy and density functional theory simulations provide evidence of Mn‐Te bonding formation in the Mn‐Si‐Te amorphous alloy, thus suggesting the role of Mn‐Te bonding in enhancing thermal stability. These findings provide a promising avenue for the advancement of novel OTS materials.This article is protected by copyright. All rights reserved.

Line-edge-roughness characterization of photomask patterns and lithography-printed patterns

This paper presents the line-edge-roughness (LER) characterization of the photomask patterns and the lithography-printed patterns by enhanced knife edge interferometry (EKEI) that measures the interferometric fringe patterns occurring when the light is incident on the patterned edge. The LER is defined as a geometric deviation of a feature edge from an ideal sharp edge. The Fresnel number-based computational model was developed to simulate the fringe patterns according to the LER conditions. Based on the computational model, the photomask patterns containing LER features were designed and fabricated. Also, the patterns were printed on the glass wafer by photolithography. The interferometric fringe patterns of those two groups of patterns were measured and compared with the simulation results. By using the cross-correlation method, the LER effects on the fringe patterns were characterized. The simulation and experimental results showed good agreement. It showed that the amplitude of the fringe pattern decreases as the LER increases in both cases: photomask patterns and printed wafer patterns. As a result, the EKEI and its analysis methods showed the potential to be used in photomask design and pattern metrology, and inspection for advancing semiconductor manufacturing processes.