Semiconductor Manufacturing Process Research Articles

Knockoff procedure for false discovery rate control in high-dimensional data streams

Motivated by applications to root-cause identification of faults in high-dimensional data streams that may have very limited samples after faults are detected, we consider multiple testing in models for multivariate statistical process control (SPC). With quick fault detection, only small portion of data streams being out-of-control (OC) can be assumed. It is a long standing problem to identify those OC data streams while controlling the number of false discoveries. It is challenging due to the limited number of OC samples after the termination of the process when faults are detected. Although several false discovery rate (FDR) controlling methods have been proposed, people may prefer other methods for quick detection. With a recently developed method called Knockoff filtering, we propose a knockoff procedure that can combine with other fault detection methods in the sense that the knockoff procedure does not change the stopping time, but may identify another set of faults to control FDR. A theorem for the FDR control of the proposed procedure is provided. Simulation studies show that the proposed procedure can control FDR while maintaining high power. We also illustrate the performance in an application to semiconductor manufacturing processes that motivated this development.

Reclaimed water in Taiwan: current status and future prospects

According to the Taiwan Water Resources Agency, Ministry of Economic Affairs, the average water demand shortage is 530.6 million m3 yr−1 during the period of 2011 to 2019, and the situation will worsen in the near future due to global climate change. Therefore, reclaimed water has been an important new water source in Taiwan, particularly for industrial consumers such as high-tech industries in Science Parks. In order to meet the targeted reclaimed water supply of 1.32 million m3 d−1 (CMD) in 2031, Taiwan is focusing on two major reclaimed water sources, including reclaimed water from high water-consuming industries and municipal wastewater treatment plants. This report reviews current technologies used for reclaimed water including units for pretreatment, desalting, polishing, and reclamation. Case studies in Taiwan including reclaimed water from high water-consuming industries such as thin film transistor-liquid crystal display (TFT-LCD) and semiconductor industries, as well as from municipal wastewater treatment plants are presented. The TFT-LCD company Innolux and semiconductor company Advaned Semiconductor Engineering have implemented total recycled water system to recycle and reclaim wastewater from manufacturing processes, achieving a total recycled water of 290 million m3 yr−1 with about 97% recovery and 3.5 million m3 yr−1 with 80% recovery, respectively. The Fengshan reclaimed water treatment plant produces 40,436 CMD reclaimed water from municipal wastewater for the China Steel Cooperation’s steel-making processes, at an overall operation and maintenance cost of 11.5 NT dollars m−3. Meanwhile the Yongkang plant produces 15,500 CMD of reclaimed water for semiconductor and TFT-LCD manufacturing processes at an overall operation and maintenance costs of 25.8 NT dollars m−3, which is due to low urea and boron limits requested by the user. Finally, challenges and future prospects for promoting the use of reclaimed water to meet the targeted supply in 2031 will be discussed.

Technology crossroads: innovation in China’s telecommunications and high-performance computer sectors threatened by US stranglehold on semiconductors

ABSTRACT Chinese companies in the computer and telecommunications sectors have been able to climb the value-added chain and become more innovative and globally competitive in part due to their ability to access global technology supply chains, many with a heavy US company presence. China’s globally active players in these sectors are reliant to some degree on US technology inputs that have now been put in jeopardy by the increasing willingness of the US government to target Chinese firms, and weaponize US company dominance of key supply chains such as software, semiconductors, and semiconductor manufacturing equipment. This paper examines prospects for Chinese companies to continue to innovate and compete globally in the computer and telecommunications sectors given the worsening geopolitical tensions centering on the technology sector.

Designing Highly Precise Overlay Targets for Asymmetric Sidewall Structures Using Quasi-Periodic Line Widths and Finite-Difference Time-Domain Simulation.

The present study introduces an optimized overlay target design to minimize the overlay error caused by asymmetric sidewall structures in semiconductor manufacturing. To achieve this goal, the overlay error formula was derived by separating the asymmetric bottom grating structure into symmetric and asymmetric parts. Based on this formula, it was found that the overlay target design with the linewidth of the bottom grating closed to the grating period could effectively reduce the overlay error caused by the sidewall asymmetry structure. Simulation results demonstrate that the proposed design can effectively control the measurement error of different wavelengths within ±0.3 nm, even under varying sidewall angles and film thicknesses. Overall, the proposed overlay target design can significantly improve the overlay accuracy in semiconductor manufacturing processes.

Bayesian Nonparametric Classification for Incomplete Data With a High Missing Rate: an Application to Semiconductor Manufacturing Data

During the semiconductor manufacturing process, predicting the yield of the semiconductor is an important problem. Early detection of defective product production in the manufacturing process can save huge production cost. The data generated from the semiconductor manufacturing process have characteristics of non-normal distributions, random missing patterns and high missing rate, which complicate the prediction of the yield. We propose the Dirichlet Process -Naive Bayes model (DPNB) that can simultaneously impute missing values and address classification problems. Since the DPNB is based on the infinite Gaussian mixture model, it can estimate complex data distributions and make predictions for missing datasets with some missing patterns due to nice properties of the Gaussian distribution. The DPNB also performs well for high missing rates since it uses all information of observed components. Experiments on various real datasets including semiconductor manufacturing data show that the DPNB has better performance than state-of-the-art methods in terms of predicting missing values and target variables as percentage of missing values increases.

Semi-Supervised Learning for Simultaneous Location Detection and Classification of Mixed-Type Defect Patterns in Wafer Bin Maps

Identifying the patterns of defective chips in wafer bin maps (WBMs) in semiconductor manufacturing processes is crucial because different defect patterns correspond to different root causes of process failures. Recently, mixed-type defect patterns (i.e., multiple defect patterns in a single wafer) have become increasingly common owing to the increased complexity of semiconductor manufacturing processes. Previous methods for classifying mixed-type defect patterns in WBMs focused on outputting only the class labels of the defect patterns and not their locations, although location information of the defect patterns is useful for tracking the root causes of failure and improving processes. Moreover, most previous methods used only labeled WBM data, although a larger quantity of unlabeled WBM data are more accessible because of the costly process of label annotation. Therefore, in this paper, we propose a semi-supervised learning method for classifying mixed-type defect patterns and detecting their locations simultaneously using both labeled and unlabeled WBM data. The proposed method extends a recent unsupervised object detection method called Attend-Infer-Repeat in a semi-supervised manner to perform object detection and classification simultaneously. The performance of the proposed method is verified using WBM datasets of different sizes. The results demonstrate the effectiveness of the proposed method for classification and location detection.

Magnetic alignment technology for wafer bonding

PurposeWafer bonding is a key process for 3 D advanced packaging of integrated circuits. It requires very high accuracy for the wafer alignment. To solve the problems of large movement stroke, position calibration error and low production efficiency in optical alignment, this paper aims to propose a new wafer magnetic alignment technology (MAT) which is based on tunnel magneto resistance effect. MAT can realize micro distance alignment and reduces the design and manufacturing difficulty of wafer bonding equipment.Design/methodology/approachThe current methods and existing problems of wafer optical alignment are introduced, and the mechanism and realization process of wafer magnetic alignment are proposed. Micro magnetic column (MMC) marks are designed on the wafer by the semiconductor manufacturing process. The mathematical model of the space magnetic field of the MMC is established, and the magnetic field distribution of the MMC alignment is numerically simulated and visualized. The relationship between the alignment accuracy and the MMC diameter, MMC remanence, MMC thickness and sensor measurement height was studied.FindingsThe simulation analysis shows that the overlapping double MMCs can align the wafer with accuracy within 1 µm and can control the bonding distance within the micrometer range to improve the alignment efficiency.Originality/valueMagnetic alignment technology provides a new idea for wafer bonding alignment, which is expected to improve the accuracy and efficiency of wafer bonding.

Densification of polycrystalline alumina with dense dislocation arrays via stainless steel sealed powder metallurgy hot isostatic press

Aluminum oxide (alumina, Al2O3) is one of the most widely used ceramic materials owing to its excellent dielectric, chemical resistance, and low cost. In contemporary semiconductor fabrication processing, in particular, Al2O3 plays a key role in high-value processing components, such as an electrostatic chuck. Here, we report for the first time a novel densifying technique for Al2O3 that can be referred to as the powder metallurgy hot isostatic press (PM-HIP) process. Unlike the conventional HIP process, our PM-HIP process can directly convert Al2O3 powders into fully densified ceramics via a one-step process. More importantly, during the PM-HIP process, thermomechanical energy can easily be transferred to each of the particles simultaneously, which facilitates the sinter process (i.e., necking and diffusion) and the clipping of lattice planes. As a result, highly dense dislocation arrays are embedded within the entire volume of the sintered body. This correlates with unique material properties-processing relationships in the Al2O3 ceramics sintered via PM-HIP. The Al2O3 ceramics sintered by PM-HIP exhibited unique mechanical and electrical properties, highlighting its potential for use in electrostatic chucks.

Classifying and clustering noisy images using subset learning based on convolutional neural networks

AbstractA high yield rate is a key factor related to success in the competitive global semiconductor manufacturing business market. Wafer bin maps (WBMs) can be used as one measure of the output quality of a semiconductor manufacturing process. A WBM is the image results from a number of circuit probe (CP) tests on a wafer after the completion of a manufacturing process. The specific defect patterns on WBMs provide crucial information for engineers to trace the causes of defects in the complicated manufacturing process. This study is aimed toward investigating major practical challenges in current WBM analyses. Our approach involved utilizing a small, carefully labeled subset to reduce the labor requirements and human recognition bias related to identification of very noisy images. The first proposed procedure classified the noisy defect patterns by using convolutional neural networks (CNNs) trained with a small subset of labeled WBMs in the early batches. The second proposed procedure provided the proper clusters of noisy defect patterns using the features extracted from the trained CNNs. This procedure made it possible to generate various clusters of WMBs and integrate them in label space. The third procedure separated the new pattern from the existing defect patterns with the help of a supplemental dataset from a similar wafer product. The evaluation of the three proposed procedures was done with simulation data generated from real sets of WBMs, which were added with random noise to maintain confidentiality. The evaluation results demonstrated the practical validity of the proposed procedures.

Higher Precision Encoder Using Hologram Scale

Semiconductor manufacturing equipment requires improvement of the accuracy by a linear encoder in a short measurement range. The error in the short range involves the interpolation error and other errors. Improvement in the interpolation error had already achieved in existing research. In contrast, this paper describes the development of a grid interferometer-type linear encoder using a hologram scale with excellent accuracy in a short measurement range. The developed encoder can achieve the error excluding interpolation error less than 10-6 magnitude per measurement range of 50 μm. In the development, error factors in the short-range measurement were examined. An equipment to identify the accuracy in this short-range measurement with high resolution and accuracy was then developed. Error analysis by the developed accuracy measurement equipment made it possible to improve a linear encoder accuracy. As a result, the accuracy of grid interferometer type linear encoder was able to reach at ±20 pm in the measurement range of 50 μm.

Semiconducting nonperovskite ferroelectric oxynitride designed ab initio

The recent discovery of HfO2-based and nitride-based ferroelectrics that are compatible to the semiconductor manufacturing process has revitalized the field of ferroelectric-based nanoelectronics. Guided by a simple design principle of charge compensation and density functional theory calculations, we discover that HfO2-like mixed-anion materials, TaON and NbON, can crystallize in the polar Pca 2 1 phase with a strong thermodynamic driving force to adopt anion ordering spontaneously. Both oxynitrides possess large remnant polarization, low switching barriers, and unconventional negative piezoelectric effect, making them promising piezoelectrics and ferroelectrics. Distinct from HfO2 that has a wide bandgap, both TaON and NbON can absorb visible light and have high charge carrier mobilities, suitable for ferroelectric photovoltaic and photocatalytic applications. This class of multifunctional nonperovskite oxynitride containing economical and environmentally benign elements offers a platform to design and optimize high-performing ferroelectric semiconductors for integrated systems.

Semi-supervised rotation-invariant representation learning for wafer map pattern analysis

Recently, data-driven approaches have been widely employed to analyze the defect patterns in wafer maps, which are crucial for identifying the root causes of failures in the semiconductor fabrication process. Representation learning embeds wafer maps into compact vector representations of useful features, based on which various downstream tasks can be performed to efficiently analyze the patterns on a large scale. If wafer maps are annotated with their defect class labels, the learned representations of wafer maps will be more informative and discriminative in defect patterns. However, the manual labeling of all wafer maps by domain experts is difficult due to practical constraints. In this study, we present a semi-supervised representation learning method that fully utilizes the information from both unlabeled and labeled wafer maps to learn better representations of wafer maps with a lower labeling cost. Given a partially labeled dataset, rotation-invariant representations of wafer maps are learned using the following three objectives. First, each unlabeled wafer map is close to any wafer map of a certain class and far from those of other classes. Second, each pair of labeled wafer maps are close to each other if they belong to the same class and are far from each other otherwise. Third, the different rotations of each wafer map are close to each other for both the unlabeled and labeled wafer maps. The effectiveness of the proposed method is demonstrated for various downstream tasks related to wafer map pattern analysis: visualization, clustering, retrieval, and classifier training.

Broadband Achromatic Metalens in the Long-Wave Infrared Regime

Compared with conventional lenses, metalenses can offer smaller form factor, light weight and new functionality, and have become the focus of the recent investigations of metasurface. To date, quite a lot of studies have been reported for chromatic aberration correction of metalenses. Noting most work was carried out to satisfy the required group delay or dispersion by introducing sophisticated and integrated nanopillars, which are obtained using computationally intensive global search algorithms. Generally, the design is time-consuming. Here, we propose an alternative scheme, where metalens that corrects the chromatic aberration can be designed by optimizing the spectral degree of freedom C(ω), rather than relying on time-consuming algorithms. The proposed metalens is compatible with the complementary metal oxide semiconductor (CMOS) fabrication process. The numerically demonstrated metalens with a diameter of 200 μm and a numerical aperture (NA) of 0.24 has a small focal length fractional change (FLFC) of 4.1% over the wavelength of 9∼12 μm with an average efficiency of 51.7% in transmission mode. Moreover, the effect of fabrication deviations on the performance of the metalens is analyzed, showing critical dimension (CD) bias, sidewall angle and pillar height all have different levels of influence on the performance of the metalens.

Distribution-free Phase-II monitoring of high-dimensional industrial processes via origin and modified interpoint distance based algorithms

Improvements in measuring devices, the development of sensing technologies, automated record-keeping and cloud storage facilities have offered us a large volume of data streams involving many variables for data-driven decision-making. Consequently, monitoring high-dimensional (HD) processes has become an essential and exciting topic in statistical process monitoring. HD monitoring poses a significant challenge because considerable uncertainty is involved in estimating process parameters when an adequately large reference sample is unavailable before monitoring. Thus, designing an effective, conveniently implementable monitoring scheme for the HD processes remains a challenging task that has yet to be effectively addressed. This paper develops two distribution-free exponentially weighted moving average (EWMA) schemes to monitor multivariate and HD processes based on origin and interpoint distances. Previous works on interpoint distance-based charts are generally not distribution-free unless only one reference point is used as a benchmark to compute the interpoint distances. We offer an improved and general way to achieve conditionally distribution-free properties closely. The proposal also combines the advantage of the nonparametric approaches for jointly monitoring the process location and scale parameters with the better shift detection performance of an EWMA scheme. The new EWMA schemes can be easily implemented even when the data dimension is large with a small number of Phase-I samples. Control limits using the median run length as a metric are evaluated and tabulated for some cases to implement the proposed chart quickly. Extensive comparative studies have been conducted to verify the efficacy of the proposed monitoring schemes. Finally, the proposed schemes are illustrated with a real problem of monitoring high-dimensional quality characteristics from semiconductor manufacturing processes.

Wafer-Scale Epitaxial Growth of an Atomically Thin Single-Crystal Insulator as a Substrate of Two-Dimensional Material Field-Effect Transistors.

As the electron mobility of two-dimensional (2D) materials is dependent on an insulating substrate, the nonuniform surface charge and morphology of silicon dioxide (SiO2) layers degrade the electron mobility of 2D materials. Here, we demonstrate that an atomically thin single-crystal insulating layer of silicon oxynitride (SiON) can be grown epitaxially on a SiC wafer at a wafer scale and find that the electron mobility of graphene field-effect transistors on the SiON layer is 1.5 times higher than that of graphene field-effect transistors on typical SiO2 films. Microscale and nanoscale void defects caused by heterostructure growth were eliminated for the wafer-scale growth of the single-crystal SiON layer. The single-crystal SiON layer can be grown on a SiC wafer with a single thermal process. This simple fabrication process, compatible with commercial semiconductor fabrication processes, makes the layer an excellent replacement for the SiO2/Si wafer.

Titanium Nitride Plasmonic Nanohole Arrays for CMOS-Compatible Integrated Refractive Index Sensing: Influence of Layer Thickness on Optical Properties

The combination of nanohole arrays with photodetectors can be a strategy for the large-scale fabrication of miniaturized and cost-effective refractive index sensors on the Si platform. However, complementary metal–oxide–semiconductor (CMOS) fabrication processes place restrictions in particular on the material that can be used for the fabrication of the structures. Here, we focus on using the CMOS compatible transition metal nitride Titanium Nitride (TiN) for the fabrication of nanohole arrays (NHAs). We investigate the optical properties of TiN NHAs with different TiN thicknesses (50 nm, 100 nm, and 150 nm) fabricated using high-precision industrial processes for possible applications in integrated, plasmonic refractive index sensors. Reflectance measurements show pronounced Fano-shaped resonances, with resonance wavelengths between 950 and 1200 nm, that can be attributed to extraordinary optical transmission (EOT) through the NHAs. Using the measured material permittivity as an input, the measured spectra are reproduced by simulations with a large degree of accuracy: Simulated and measured resonance wavelengths deviate by less than 10 nm, with an average deviation of 4 nm observed at incidence angles of 30° and 40°. Our experimental results demonstrate that an increase in the thickness of the TiN layer from 50 to 150 nm leads to a sensitivity increase from 614.5 nm/RIU to 765.4 nm/RIU, which we attribute to a stronger coupling between individual LSPRs at the hole edges with spatially extended SPPs. Our results can be used to increase the performance of TiN NHAs for applications in on-chip plasmonic refractive index sensors.

Human–machine collaboration for improving semiconductor process development

One of the bottlenecks to building semiconductor chips is the increasing cost required to develop chemical plasma processes that form the transistors and memory storage cells1,2. These processes are still developed manually using highly trained engineers searching for a combination of tool parameters that produces an acceptable result on the silicon wafer3. The challenge for computer algorithms is the availability of limited experimental data owing to the high cost of acquisition, making it difficult to form a predictive model with accuracy to the atomic scale. Here we study Bayesian optimization algorithms to investigate how artificial intelligence (AI) might decrease the cost of developing complex semiconductor chip processes. In particular, we create a controlled virtual process game to systematically benchmark the performance of humans and computers for the design of a semiconductor fabrication process. We find that human engineers excel in the early stages of development, whereas the algorithms are far more cost-efficient near the tight tolerances of the target. Furthermore, we show that a strategy using both human designers with high expertise and algorithms in a human first–computer last strategy can reduce the cost-to-target by half compared with only human designers. Finally, we highlight cultural challenges in partnering humans with computers that need to be addressed when introducing artificial intelligence in developing semiconductor processes.

In Situ Plasma Impedance Monitoring of the Oxide Layer PECVD Process

The use of plasma in semiconductor fabrication processes has been continuously increasing because of the miniaturization of semiconductor device structure, and plasma enhanced chemical vapor deposition (PECVD) has become a major process in thin film deposition. As a consequence, plasma diagnosis has become crucial during the deposition process, but the lack of in situ plasma monitoring sensors requires further development of existing in situ sensors, such as the Langmuir probe and optical emission spectroscopy (OES), for in situ plasma process monitoring. In this study, electrically equivalent circuit models of the PECVD chamber functioned as a plasma impedance model with respect to the deposited thin film thickness while plasma impedance was measured using a radio frequency voltage–current (VI) probe. We observed a significant correlation between the deposited film thickness of the chamber wall and the measured impedance of the PECVD chamber cleaning application in the semiconductor industry.

공간형 위치 결정 스테이지를 위한 타원형 및 포물선형 2 자유도 플렉셔 힌지에 대한 해석

With advancements in semiconductor manufacturing processes and the development of precision processing technology, flexure hinge-based ultra-precision positioning stages are widely used. In the flexure hinge, axial and bending stiffness properties greatly influence positioning performance. This study examined the stiffness properties of elliptic and parabolic 2-degrees-of-freedom (DOF) hinges, which have not been extensively discussed. The Timoshenko beam theory was applied to derive the stiffness equations for the axial and bending directions of each hinge. The stiffness properties were examined in several design conditions by comparing theoretical and finite element analyses. Based on the results of the analyses, an empirical formula in exponential form for the design of an elliptic hinge was constructed through surface-fitting. The elliptic hinge was found to be a better alternative to a circular hinge under certain design conditions by adjusting two design parameters. In the future, we will develop sophisticatedly designed hinges with improved axial and bending stiffness properties compared to the existing circular and elliptic hinges.

Single-Electron Transport and Detection of Graphene Quantum Dots

The integrated structure of graphene single-electron transistor and nanostrip electrometer was prepared using the semiconductor fabrication process. Through the electrical performance test of the large sample number, qualified devices were selected from low-yield samples, which exhibited an obvious Coulomb blockade effect. The results show that the device can deplete the electrons in the quantum dot structure at low temperatures, thus, accurately controlling the number of electrons captured by the quantum dot. At the same time, the nanostrip electrometer coupled with the quantum dot can be used to detect the quantum dot signal, that is, the change in the number of electrons in the quantum dot, because of its quantized conductivity characteristics.