Semiconductor Industry Association Research Articles

Status and review of two-dimensional carrier and dopant profiling using scanning probe microscopy

An overview of the existing two-dimensional carrier profiling tools using scanning probe microscopy includes several scanning tunneling microscopy modes, scanning capacitance microscopy, Kelvin probe microscopy, scanning spreading resistance microscopy, and dopant selective etching. The techniques are discussed and compared in terms of the sensitivity or concentration range which can be covered, the quantification possibility, and the final resolution, which is influenced by the intrinsic imaging resolution as well as by the response of the investigated property to concentration gradients and the sampling volume. From this comparison it is clear that, at present, none of the techniques fulfills all the requirements formulated by the 1997 Semiconductor Industry Association roadmap for semiconductors [National Technology Roadmap for Semiconductors (Semiconductor Industry Association, San Jose, CA, 1997)]. Most methods are limited to pn-junction delineation or provide a semiquantitative image of the differently doped regions. However, recent comparisons have shown that the techniques can provide useful information, which is not accessible with any other method.

The Use of Trade Association Disclosures by Investors and Analysts: Evidence from the Semiconductor Industry*

AbstractThis paper investigates the relation between industry‐wide information disclosures by the trade association for the semiconductor industry and both share prices and analyst forecasts. Such disclosures may have little impact on investors and analysts, since prior theoretical research suggests that trade associations may be unable to secure reliable data from firms in an industry. At the same time, such disclosures may be important, since prior empirical research suggests that share prices and analyst forecasts reflect industry‐wide earnings effects earlier than firm‐specific effects. We document significant stock price movements on release dates of industry Flash Reports by the Semiconductor Industry Association (SIA) each month that contain aggregate industry data on new orders and shipments. The magnitude of the price revisions on Flash Report disclosure dates is positively associated with changes in the numbers disclosed and varies across sample firms in a manner associated with identifiable characteristics of the firms. Further tests indicate that the Flash Report provides mainly forward‐looking information on new orders that is linked to firm‐specific sales changes and has explanatory power for quarterly stock prices beyond firm‐specific earnings. This information is used by security analysts mainly in assessing the persistence of firm‐specific quarterly sales changes. Our findings support the hypothesis that the SIA is able to obtain data from firms, compile it into reliable aggregate statistics, and then distribute these statistics in a timely fashion.

WHEN THE CHIPS ARE DOWN

The global semiconductor industry is gradually coming out of a sharp downturn that plagued it during 1998 and much of 1999. The recovery is good news, but for the chemical companies that supply semiconductor makers with crucial raw materials, life after the downturn just isn't the same. Global semiconductor sales fell 8% last year to $125 billion, according to the Semiconductor Industry Association, San Jose, Calif., as the Asian economic crisis and general market softness took their toll. The situation was even more dire among suppliers of equipment and materials to the semiconductor industry, with 1998 sales plummeting 21% to $21.8 billion, according to Semiconductor Equipment & Materials International (SEMI), Mountain View, Calif. In contrast, this year is turning up nicely. After a slow start, worldwide semiconductor sales in 1999 are expected to end 12% higher than last year, and equipment and materials sales should grow by 9%. Even rosier forecasts are being made for ...

Lithography for sub-60 nm resist nanostructures

As the semiconductor community continues to follow the Semiconductor Industry Association Roadmap, resist structures are being printed further into the nanometer domain. However, a persistent issue for successful sub-60 nm resist patterning is mechanical stability at high aspect ratios. The objective of this article is to understand what processing conditions facilitate processing resist nanostructures with useful aspect ratios for the fabrication of sub-60 nm transistors. We have found that, in aqueous based development and rinse, if the resist thickness is reduced, then the aspect ratio is sacrificed for the sake of resolution. The implication is that there is a resolution limit at which resist structures will have aspect ratios that are useful for device fabrication. We have also found that there are development effects that occur in the thick film regime that are not reproducible with thin films. The best resolution structures we have been able to print are lines of 28 nm in width using direct write electron-beam lithography on negative chemically amplified resists NEB-22 and NEB-31 (Sumitomo Chemical Inc.) with an aspect ratio of about 3. To put this result in perspective, this is about 40 molecules wide.

Specular electron scattering in metallic thin films

Specular electron scattering at the surface of metallic thin films is an important phenomenon for a class of magnetic multilayers known as giant magnetoresistance (GMR) spin valves. In the very best GMR spin valves, a significant part of the GMR effect is attributable to specular electron scattering. We have investigated the importance of specular electron scattering by developing surface-modification techniques that produce diffuse electron scattering. We have used these techniques to investigate specular electron scattering in GMR spin valves and in pure metals. Some of the largest effects are found in Au films. It is noted that specular electron scattering will be a highly desirable property in future generations of microelectronic interconnects as the feature size approaches the mean free path of the conduction electrons. In order to meet the Semiconductor Industry Association Roadmap requirements for interconnect resistivity, interconnects with highly specular surfaces must be developed.

Deep submicron microprocessor design issues

Deep-submicron technology allows billions of transistors on a single die, potentially running at gigahertz frequencies. According to Semiconductor Industry Association (SIA) projections, the number of transistors per chip and the local clock frequencies for high-performance microprocessors will continue to grow exponentially in the near future. This ensures that future microprocessors will become ever more complex. However, physical and program behavioral constraints will limit the usefulness of this complexity. Physical constraints include interconnect and device limits, as well as practical limits on power and cost. Program behavioral constraints result from program control and data dependencies, and from unpredictable events during execution. Other challenges include the need for advanced CAD tools to combat the negative effect of greater complexity on design time. Designers will also have to make improvements to preserve computational integrity, reliability, and diagnostic features. Successful implementations will depend on the processor architect's ability to foresee technology trends and understand the changing design trade-offs for specific applications, beginning with the differing requirements for client versus server processors. This article discusses these trade-offs in light of industry projections and the many considerations affecting deep submicron technology.

Taking Moore's law into the next century

The Semiconductor Research Corp. is one of the few organizations to get fierce competitors like Intel, Motorola, and IBM to the same table, let alone cooperate, and it has also wrangled money-$37 million annually-from these companies and others. With this money, it funds future research to keep the engines of semiconductor production churning. In short, the SRC is bent on taking Moore's law into the next century by coordinating "precompetitive" academic research to meet industry's needs. Together with its sister organizations-the Semiconductor Industry Association and Sematech-SRC helps chart and promote the continued progress of the semiconductor industry. Their main tool for doing so is the National Technology Roadmap for Semiconductors. Published every two years, this document outlines research areas that need attention so that the industry can maintain the pace of semiconductor production. This article discusses two of those areas-interconnects, and design and test-in depth.

IC design on the World Wide Web

A design log-jam is imminent. By 2001, designers of a single application-specific IC may have over 100 million transistors at their beck and call, according to the US Semiconductor Industry Association's National Roadmap for Semiconductors. Chip designs will rarely be home grown-instead, they will be organized around elements the design team acquires from others, either from companies that specialize in developing so-called intellectual property or from the reuse of blocks previously developed within the same or another organization. This paper describes how the rising tide of Web-based tools and services augurs the next sea change in electronic design.

Developments in equipment support technology

This article will review the achievements, on-going development activities and needs in “equipment support technology,” i.e., the critical or key components which surround the process chamber and without which an effective process cannot be reliably and repeatably executed. The challenges of the SIA (Semiconductor Industry Association) Roadmap have been the focus for the dramatic developments in many areas, such as the following: delivery of process material vapors into the reactor, control of the exhaust effluent from the reactor, on-process pressure measurement and control sensors and actuators, implementation of a well supported digital sensor bus introduced on 300 mm tool sets, tool and process diagnostics through residual gas analysis, and the incorporation of fault detection schemes and the eventual implementation of model based process control techniques. With the escalating cost of wafers-in-process, and the desire to increase overall equipment effectiveness and reduce cost-of-ownership, it becomes increasingly important to separate, control, diagnose and predict the behavior of critical process variables in real time. In-situ measurement, control, and metrology result in dramatically improved meantime between failures, shorter meantime to repair, and a significantly reduced cost per measurement function.

Reliability and Lifing Methodologies for Microelectronic Systems

ABSTRACTIntegration of core electronic functions is progressing at a remarkable rate. The high-end computers that we are using now may be available on a single die by the turn of the century. The effect of this, and other advances on semiconductor assembly and packaging has generated the need for integrated component-level electrical thermal, and mechanical models and simulation methods, as described in the Semiconductor Industry Association national Technology Roadmap for Semiconductors. Although corporate and university research and development in the semiconductor area is intense (there are eight major university-based packaging centers around the world, for example), design/development methodologies that consider the combined and interactive effects of mechanical, thermal and chemical conditions on the reliability and durability of integrated components have been slow to develop. However, such methodologies have been developed for applications of complex composite systems in various other technologies where the operating conditions are similar. The present paper will discuss those developments and the possibility of applying that technology to microelectronic systems.

Potentials and challenges for lithography beyond 193 nm optics

The growth of the semiconductor industry continues to be driven to a large extent by steady advances in microlithography. Renewal of the Semiconductor Industry Association Roadmap is underway and accelerating requirements are predicted. The 130 nm generation is anticipated to be available in the year 2003, but the path to get there is not obvious. To meet the needs of its members, SEMATECH is embarking on a program to explore and narrow the technology options on the roadmap. The goal is to make a data-driven decision by late 1997. As an introduction to this Special Session on 0.13 Micron Lithography for Manufacturing, this article reviews the Lithography Technology Working Group requirements and potential solutions for roadmaps. The SEMATECH program to narrow the options beyond 193 nm optics is presented in detail, including the critical issues for each technology.

Stock Price Effects of U.S. Trade Policy Responses to Japanese Trading Practices in Semi-Conductors

Over much of the last decade, the United States and Japan have been embroiled in a trade dispute over access to Japanese markets for semiconductors and downstream products. This study examines stock price reactions for firms affected by a subset of events commencing with the filing of a Section 301 petition by the U.S. Semiconductor Industry Association alleging unfair practices by the Japanese and culminating in the 1986 Trade Agreement. The evidence suggests that U.S. semiconductor consumers as well as producers benefited from these events.

The Semiconductor Industry—Model for Industry/University/Govemment Cooperation

OVERVIEW:Semiconductor companies have joined forces to address a variety of industry-wide problems. The first step was the formation of the Semiconductor Industry Association (SIA) in 1977 to work on common environmental issues. The Association worked closely with the federal government to resolve an adverse competitive situation vis à vis Japanese companies. In 1982, the SIA formed the Semiconductor Research Corporation with dual objectives of developing highly qualified technical personnel for employment in the industry and conducting a program of long-range, pre-competitive research and technology development. The program is carried out at a large number of universities, and is unique in its industry/university relations. Subsequently, in 1987, a corporation for conducting technology development, primarily by industry, SEMATECH, was formed. Finally, to guide the research funded by these two corporations, the SIA produced the Semiconductor Technology Roadmap, with the technical contributors coming from industry, academia and government. This comprehensive set of initiatives has resulted in excellent working relations with government and utilization of the university community, in addition to technology developed for the benefit of SIA members. This initiative can also serve as a model for other industries.

Industry roadmaps: The challenge of complexity

The history of VLSI, has been marked since the early 70′s, by an exponential growth rate, with a new generation appearing every three years. Recent announcements by major manufacturers confirm this trend, and the Semiconductor Industry Association has tried, in a recent study, to extrapolate it to year 2010, evidencing the major constraints and the critical issues. However, if we take as an example the roadmap of the Flash memories, which will be one of the major device families around year 2000, we can see potentially critical issues that could slow down the growth rate: on one side the increased circuit complexity will force to push defect density down to values that are hardly conceivable today, on the other side the increasing cost of facilities, coupled to a constant reduction of the price/implemented function will strongly affect the picture of the semiconductor industry, drastically reducing the number of major players. In order to stay competitive, semiconductor industry must take advantage of new equipment to pursue a program of constant product shrink and yield increase, turning rapidly into profit the huge investments for new equipment. Furthermore, the increase in equipment costs will reduce the number of equipment manufacturers, and their willingness to commit to expensive development programs will be conditioned by the presence of clear strategies on the side of silicon manufacturers.

Credible Disclosure of Industry-Wide Information Through Trade Associations: Evidence from the Semiconductor Industry

Prior analytical research suggests that competitive firms within an industry may not voluntarily share their private market information through a trade association. Given legal restrictions which preclude trade associations from compelling participation or accurate reporting by firms or revealing their proprietary data, it is uncertain whether trade associations can design and implement systems to collect and transmit useful market information. This paper documents significant stock price movements on release dates of aggregate industry data on new orders and shipments by the Semiconductor Industry Association (SIA) each month which are positively associated with changes in the numbers disclosed. The industry information released is positively correlated with earnings changes in the subsequent quarterly earnings announcements of firms within the industry. Additional tests indicate that semiconductor firms? stock prices respond significantly to their quarterly earnings announcements, and that the prior disclosure of aggregate industry information does not materially reduce the valuation relevance of earnings reports of semiconductor firms . Overall, these findings support the hypothesis that trade associations are able to obtain reliable data from firms, aggregate it into statistics that do not reveal a specific company?s information, and then distribute aggregate statistics back to participating firms in a timely manner. Our analysis further suggests that while the aggregate industry data are informative for investors in high-tech stocks, they do not reduce the valuation impact of semiconductor firms? quarterly earnings.

Solid state [Trends/developments

As linewidths and other lithographic features of ICs shrink, and the number of transistors on a chip mushrooms, functions galore are being combined on a single die. The ultimate result of this trend will be the system-on-a-chip, in which all circuitry-for a computer, a cellular phone, a microelectromechanical actuator, or a solid-state camera-will be housed within a couple of square centimeters of silicon. The Semiconductor Industry Association, San Jose, California, predicts that the trend toward greater complexity will endure throughout this decade and the next. Nonetheless, to keep the technology moving onward, the association's National Technology Roadmap for Semiconductors, finalized late in 1994, identified many key advances as prerequisites to progress. These are: power management, optical techniques for IC production, interconnect technology, and environmental factors. Some of the development highlights discussed are powerful multimedia engines, graphics united with main memory, and DRAM with on-board microprocessors.

Chemical-Mechanical Planarization of Aluminum-Based Alloys for Multilevel Metallization

As recently as 1993, the prevailing presumption among the semiconductor technical community was that then-current development efforts associated with aluminum lines and tungsten damascene vias needed to shift rapidly to copper multilevel interconnect schemes. This is exemplified by the June 1993 issue of the MRS Bulletin, which featured copper metallization as its theme. In the intervening years, however, that same technical community revised the Semiconductor Industry Association (SIA) roadmap and placed renewed emphasis on the use of an all-aluminum interconnect scheme. This was done largely in deference to the costs associated with converting existing semiconductor lines to copper-compatible facilities. In addition to tooling costs, there is a learning curve for copper systems that remains to be established for device reliability, field failures, yield learning, and process maturation. On the other hand, existing fabs are already compatible with aluminum metallurgies, and there is a rich history of reliability and yield data.This change in direction creates two immediate needs: (1) the need to fill small-diameter vertical interconnects (vias) with void-free aluminum and (2) the need to remove the top surface aluminum resulting from its blanket deposition (overburden) following the metal fill. In addition, for high circuit-density applications, it may be desirable, if not necessary, to form the metal lines using the same damascene fill method as is used for the vias. This process strategy replaces metal etching and insulator gap fill with insulator (usually silicon oxide) etching and metal gap fill.

Error budget analysis of the SCALPEL(R) mask for sub-0.2 μm lithography

In this article we derive the design constraints, and hence the fabrication requirements, for the SCALPEL(R) mask for sub-0.2 μm design rules. These are determined by the Semiconductor Industry Association (SIA) advanced mask specifications, in combination with the likely error budget of an advanced pattern generator. Further constraints are imposed by the overall SCALPEL system error budget. We demonstrate that the mask is not only technically feasible to construct, but also that it can be fabricated at an acceptable cost.

Photocatalytic oxidation for point-of-use abatement of volatile organic compounds in microelectronics manufacturing

In gas–solid heterogeneous photocatalytic oxidation (PCO), volatile organic compounds (VOCs) present in process air or air vents can be rapidly and completely oxidized to innocuous by-products over a near-ultraviolet (UV) illuminated titanium dioxide thin film catalyst at room temperature. This class of advanced oxidation processes appears to be well-suited for point-of-use VOC abatement in the microelectronics manufacturing industry. In this article, we review industrial requirements and unresolved technical issues in the context of the recently published Semiconductor Industry Association roadmap. The specific requirements for VOC abatement from a typical photolithography track are presented. Bench-scale PCO kinetics for target VOCs are reviewed to demonstrate the typical process behavior expected.

Barriers Against Copper Diffusion into Silicon and Drift Through Silicon Dioxide

The Semiconductor Industry Association (SIA) roadmap calls for the incorporation of Cu plugs (vias) integrated with interconnects in 1997. Copper is being evaluated for ULSI metallization because of its lower bulk electrical resistivity and its superior resistance to electromigration and stress voiding as compared to commonly used aluminum and its alloys. One of the major drawbacks of Cu is its fast diffusion in Si and drift in SiO2-based dielectrics, resulting in the deterioration of devices at low temperatures. Hence a diffusion barrier is necessary between Cu and Si or SiO2. Figure 1 is a cross section ofa three metal level interconnect structure using Cu as the conductive material. The interlevel dielectrics (ILD) could be conventional SiO2-based materials or more ideally, materials with low dielectric constants such as polyimide. If conventional SiO2 is used, then Cu plugs and interconnects have to be enclosed in diffusion/drift barriers so that Cu will not move into Si or SiO2 under thermal stress or biased temperature stress (BTS).This article reviews the published studies on conductive diffusion barriers between thin Cu films and Si substrates. In addition, the work on diffusion and drift of Cu into commonly used inorganic dielectric systems is also summarized. Finally, some concerns involving diffusion/drift barriers between Cu and Si or SiO2 for sub-0.5 μm feature size with high aspect ratios are discussed.