Chemical-Mechanical Planarization of Aluminum-Based Alloys for Multilevel Metallization

Abstract

As recently as 1993, the prevailing presumption among the semiconductor technical community was that then-current development efforts associated with aluminum lines and tungsten damascene vias needed to shift rapidly to copper multilevel interconnect schemes. This is exemplified by the June 1993 issue of the MRS Bulletin, which featured copper metallization as its theme. In the intervening years, however, that same technical community revised the Semiconductor Industry Association (SIA) roadmap and placed renewed emphasis on the use of an all-aluminum interconnect scheme. This was done largely in deference to the costs associated with converting existing semiconductor lines to copper-compatible facilities. In addition to tooling costs, there is a learning curve for copper systems that remains to be established for device reliability, field failures, yield learning, and process maturation. On the other hand, existing fabs are already compatible with aluminum metallurgies, and there is a rich history of reliability and yield data.This change in direction creates two immediate needs: (1) the need to fill small-diameter vertical interconnects (vias) with void-free aluminum and (2) the need to remove the top surface aluminum resulting from its blanket deposition (overburden) following the metal fill. In addition, for high circuit-density applications, it may be desirable, if not necessary, to form the metal lines using the same damascene fill method as is used for the vias. This process strategy replaces metal etching and insulator gap fill with insulator (usually silicon oxide) etching and metal gap fill.