Semiconductor-insulator Interface Research Articles

Bias stress effect in polyelectrolyte-gated organic field-effect transistors

A main factor contributing to bias stress instability in organic transistors is charge trapping of mobile carriers near the gate insulator-semiconductor interface into localized electronic states. In this paper, we study the bias stress behavior in low-voltage (p-type) polyelectrolyte-gated organic field effect transistors (EGOFETs) at various temperatures. Stressing and recovery in these EGOFETs are found to occur six orders of magntiude faster than typical bias stress/recovery reported for dielectric-gated OFETs. The mechanism proposed for EGOFETs involves an electron transfer reaction between water and the charged semiconductor channel that promotes the creation of extra protons diffusing into the polyelectrolyte.

Measurement of effective carrier lifetime at the semiconductor–dielectric interface by Photoconductive Decay (PCD) Method

The semiconductor–dielectric interface is of key importance to the performance of Metal-Oxide-Semiconductor transistors (MOSFETs). The near-surface Photoconductance Decay (ns-PCD) method using probe contacts is shown in this study to be very useful in measuring effective carrier lifetime at the semiconductor–dielectric interface. By doing so, it provides direct information on the condition of the charge transport environment in the MOSFET channel without a need to fabricate a transistor. The way measurement is implemented depends on the thickness of dielectric. For dielectric layers thicker than about 5nm, etched windows in the dielectric layer are necessary to achieve an ohmic contact with the semiconductor layer. For dielectric layers thinner than about 5nm, however, the ohmic contact to the semiconductor substrate, essential to the performance of this measurement, is established using probes and electrical contact formation process. The measurements were performed on thermally oxidized Si–SiO2 structures as well as Si–Al2O3 (3nm) and Si–Ta2O5 (3nm) structures formed by means of Atomic Layer Deposition (ALD). The results obtained demonstrate that the PCD method adapted as discussed in this work can be very useful in monitoring condition of semiconductor – ultra-thin (<5nm) dielectric interface by measuring carrier lifetime in the as-processed samples, i.e. without subjecting it to any processing step beyond dielectric deposition.

Efficient Characterization of Threshold Voltage Instabilities in SiC nMOSFETs Using the Concept of Capture-Emission-Time Maps

We utilize the recently suggested capture-emission-time (CET) maps for the first time for SiC technologies. CET maps are a very powerful characterization technique which allow the elegant and comprehensive analysis of oxide/interface traps at or near the semiconductor-dielectric interface and were originally developed to characterize degradation of Si based MOSFETs. For as-processed SiC MOSFETs we present first results of the SiC-SiO2 interface using CET maps. We suggest that oxide traps are mainly responsible for the instability in SiC MOSFETs. Furthermore we state that the large time constants and the temperature activation of the traps in SiC MOSFETs can be consistently explained when accounting for multi-phonon processes for the microscopic charge exchange. A recently suggested model including such microscopic transitions is applied to SiC MOSFETs and shown to reproduce our experimental data with high accuracy for a large temperature range.

Fluctuation analysis of an organic semiconductor–insulator interface

The space-charge region of an organic semiconductor (OS)-insulator interface is probed by analyzing the spontaneous, thermally driven drain current fluctuations of a field-effect transistor in which the OS forms the gate electrode. This so called "excess drain current noise" is the outcome of local fluctuations of the Fermi level, resulting from stochastic exchange of electrons between traps near the Fermi level. The power spectral density of this noise is characteristic of a Lorentzian process with a distribution of time constants, which is attributed to the disorder in the OS film. Furthermore, this disorder leads to local inhomogeneity of the work function in the film and a finite correlation length of the work function fluctuations. The measurement of work function noise is only possible within a correlation length of the OS-insulator interface. Through systematic variation of gate voltage, primary doping and secondary doping levels, the correlation length, disorder, and the trapping/de-trapping time constant are examined on polyaniline as a representative OS. A model is proposed for local work function variations and spontaneous charge-carrier fluctuations within polyaniline films with consequences for organic electronics using organic semiconductors.

High performance organic field-effect transistors using cyanoethyl pullulan (CEP) high-k polymer cross-linked with trimethylolpropane triglycidyl ether (TTE) at low temperatures

Low-voltage operable organic field-effect transistors (OFETs) were fabricated using a low-temperature curable high-k polymer cyanoethyl pullulan (CEP) as a gate insulator with trimethylolpropane triglycidyl ether (TTE) as a crosslinking agent. With this crosslinking agent, the gate insulators showed low leakage current and a high dielectric constant of 14.8–16, and most importantly, could be cured at low temperatures around 100 °C, which is compatible with most plastic substrates for future plastic electronics. The favorable semiconductor–dielectric interface was obtained due to the surface alignment of well-packed pentacene domains, which enabled excellent transistor performance, with one of the highest mobilities around 6 cm2 V−1 s−1, an on/off current ratio (Ion/Ioff) ∼105, and a steep subthreshold (SS) ∼0.095 V dec−1. The high mobility was found to be closely correlated with the surface CN dipole density rather than other possibilities, such as dielectric roughness and surface energy. The initial growth of the semiconductors was also studied and correlated with the affecting variables.

Current spreading effects in fully printed p-channel organic thin film transistors with Schottky source–drain contacts

Contact effects have been analyzed, by using numerical simulations, in fully printed p-channel OTFTs based on a pentacene derivative as organic semiconductor and with Au source/drain contacts. Considering source–drain Schottky contacts, with a barrier height of 0.46eV, device characteristics can be perfectly reproduced. From the detailed analysis of the current density we have shown that current spreading occurs at the source contact, thus influencing the effective contact resistance. At low Vds and for a given Vgs, the current is mainly injected from an extended source contact region and current spreading remains basically constant for increasing Vds. However, by increasing Vds the depletion layer of the Schottky contact expands and reaches the insulator–semiconductor interface, causing the pinch-off of the channel at the source end (Vdsat1). For Vds>Vdsat1 the current injected from the edge of the source contact rapidly increases while the current injected from the remaining part of the source contact basically saturates. Current spreading shows a Vgs-dependence, since the contact injection area depends on the channel resistance and also barrier lowering of the Schottky source contact depends upon Vgs. The injected current from the edge of the source contact can be reproduced using the conventional diode current expression, assuming a constant value for the zero barrier lowering saturation current and considering a Vgs-dependent barrier lowering. The presented analysis clarifies the Vgs-dependence of the contact current–voltage characteristics and points out that the I–V contact characteristics cannot directly be related to a single diode characteristics. Indeed, the contact characteristics result from the combination of two rather different regimes: at low Vds the current is injected from an extended source contact region with a current spreading related to Vgs, while for Vds above the pinch-off of the channel at source end, the current is injected primarily from the edge of the source contact and is strongly enhanced by the barrier lowering.

Copper nano composites functionalized by bis-benzimidazole diamide ligand: Effect of size, co-anion dependent conductivity and band gap studies

Copper (I) and copper (II) nano composites capped with a bis-benzimidazole diamide ligand were prepared by reverse micelle method and characterized using CHNS, FTIR, 1H NMR, TEM and DLS studies. All particles were spherical ranging between 10 and 70 nm. They displayed a quasi reversible redox wave due to the Cu (II)/Cu (I) reduction process. The Eg1′ values shift anodically as NO3− < Cl− < SCN−. Electrochemical HOMO and LUMO band gap (Eg1′) for the nano composites were +1.80 (NO3−), +2.80 (Cl−) and +4.10 (SCN−) eV, respectively. However, the optical band gap (Eg1) for the nano composites was calculated from their absorption edges and lie between 1.77 and 4.13 eV. Fluorescence studies reveal that nano composites in themselves behave as an enhancer and quencher in respect to ligand, Quantum yield (φ) is varying from 0.008 to 0.02 photon. The activation energies range from 34 to 54 kJ mol−1 and are quite low in comparison to that of the free bis-benzimidazole diamide ligand (137 kJ mol−1). The lower activation energies further re-emphasize the nano size of these composites. At room temperature, the dc conductivity lies between 1 × 10−4–9.33 × 10−4 S cm−1 [NO3− > SCN− > Cl−] indicating them to be on the semiconductor insulator interface. The dielectric constant, dielectric loss and the ac conductivity were measured for all nano at room temperature and below the room temperature for the nano composite containing nitrate as co-anion. The conductivity was found to follow the correlated barrier hopping (CBH) mechanism; the exponent factor (s) varies from 0.5 to 1.

Analytic potential and charge model for III-V surrounding gate metal-oxide-semiconductor field-effect transistors

In this work, an analytical model is proposed to calculate the potential and the inversion charge of III-V cylindrical Surrounding-Gate metal-oxide-semiconductor field-effect transistors (MOSFETs). The model provides expressions for the calculation of the subband energies and their corresponding wavefunctions, taking into account their penetration into the gate insulator and the effective mass discontinuity in the semiconductor-insulator interface for this kind of devices. The model considers Fermi-Dirac statistics and the two-dimensional quantum confinement of the carriers. We demonstrate that our analytical solution fits very well the numerical solution in all operating regimes and for different device sizes and materials.

Tuning the Thermoelectric Properties of Conducting Polymers in an Electrochemical Transistor

While organic field-effect transistors allow the investigation of interfacial charge transport at the semiconductor-dielectric interface, an electrochemical transistor truly modifies the oxidation level and conductivity throughout the bulk of an organic semiconductor. In this work, the thermoelectric properties of the bulk of the conducting polymer poly(3,4-ethylenedioxythiophene)-poly(styrene sulfonate) were controlled electrically by varying the gate voltage. In light of the growing interest in conducting polymers as thermoelectric generators, this method provides an easy tool to study the physics behind the thermoelectric properties and to optimize polymer thermoelectrics.

Investigation on bias stress effects in n-type PDI8-CN2 thin-film transistors

In this contribution, we investigate the bias stress phenomenon in n-type PDI8-CN2 thin-film transistors fabricated by evaporation on both bare and hexamethyldisyloxane (HMDS)-treated SiO2 gate dielectrics. Since the morphological properties of PDI8-CN2 films are poorly influenced by the SiO2 treatment, all the differences observed in the DC electrical response and the bias stress performances of these devices can be mainly ascribed to the interface chemistry between the dielectric and the semiconductor. In long-term bias stress experiments, performed in vacuum keeping the devices under fixed voltage polarization, the IDS(t) decaying behavior shows to saturate when transistors on HMDS-treated substrates were considered. According to our findings, the BS physical origin is related to the occurrence of electrochemical reactions where PDI8-CN2 molecules interact with H2O, producing O2 and protons (H+) which can initially diffuse in the SiO2 layer barrier. Hence, the possibility that the bias stress effect in these n-type devices can be ruled by the H+ back-diffusion process, occurring from the SiO2 bulk towards the dielectric-semiconductor interface during the prolonged application of positive VGS voltages, is discussed.

Tunneling currents in a spherically shaped MIS structure

The tunneling currents flowing in a spherically shaped metal–insulator–semiconductor structure with a tunnel-thin insulating layer are calculated and compared to those in an ordinary planar structure. Both electron and hole components as well as the band-to-band carrier transport are considered. In general, a spherical system behaves like a planar one with higher, than specified, semiconductor doping level. Operation of a bistable tunnel emitter transistor on n-Si is analyzed in detail; it is shown that the switching voltage is reduced with decreasing insulator–semiconductor interface radius. The geometry effects come into play for the radii below 100–200 nm. Some experimental pieces of evidence for these effects are briefly discussed.

Effect of interface charge on the dc bias stress-induced deformation and shift of the transfer characteristic of amorphous oxide thin-film transistors

The presence of a deformation or hump in the subthreshold region of the transfer characteristic of Amorphous Oxide Semiconductor (AOS) Thin-Film Transistors (TFTs) has been observed after DC stress and related to different causes. In previous works, it has been shown that in devices with active-layer thickness greater than 120nm, a region with relatively high conductivity remains near the back interface of the active layer, providing a parallel current path between drain and source giving rise to this deformation. If this is the cause of the hump, it should be present independently of bias stress. However, experiments show that the hump is observed in AOS TFTs with active layer thickness below 120nm and only after DC stress. In this work we show that, if during DC bias stress, the density of positively charged states at the interface between the active layer and the passivation layer of an AOS TFT becomes high enough to provide a parallel conduction path, the deformation or hump in the transfer curve can appear. This condition is more likely to occur in devices passivated with dielectrics that can present charged traps at the dielectric–semiconductor interface and agrees well with experimental data reported for AOS TFTs.

Fixed negative interface charges compromise organic ferroelectric field-effect transistors

Capacitance–voltage (C–V) and current–voltage measurements have been undertaken on metal-ferroelectric-semiconductor capacitors and ferroelectric field-effect transistors (FeFETs) using the ferroelectric polymer poly(vinylidenefluoride-trifluoroethylene) as the gate insulator and poly(3-hexylthiophene) as the active semiconductor. C–V measurements, voltage-dependence of gate currents and FeFET transfer characteristics all confirm that ferroelectric polarization is stable and only reverses when positive/negative coercive fields are exceeded for the first time. The apparent instability observed following the application of depletion voltages arises from the development of a negative interfacial charge which more than compensates the ferroelectric-induced shift, resulting in a permanent shift in threshold voltage to positive values. Application of successive bipolar voltage sweeps to a diode-connected FeFET show that significant remanent polarization is only induced in an unpoled device when the coercive field is exceeded during the first application of accumulation voltages. This initial polarization and its growth during subsequent bipolar voltage sweeps is accompanied by the accumulation of the fixed interfacial negative charges which cause the positive turn on voltages seen in C–V and transfer characteristics. The origin of the negative charge is ascribed either to layers of irreversible ferroelectric domains at the insulator surface or to the drift to the insulator-semiconductor interface of F- ions produced electrolytically during the application of accumulation voltages.

Facile synthetic route to implement a fully bendable organic metal–insulator–semiconductor device on polyimide sheet

Triblock copolymer surfactant, HO(CH2CH2O)20(CH2CH(CH3)O)70(CH2CH2O)20H (i.e. P123)-based nanocrystalline (nc)-TiO2 thin film had been synthesized on organic flexible polyimide (PI) sheet for their application in organic metal–insulator–semiconductor (MIS) device. The nc-TiO2 film over PI was successfully deposited for the first time by a systematic solution proceeds dip-coating method and by the assistance of triblock copolymer surfactant. The effect of annealing temperature (270°C, 5h) on the texture, morphology and time-induced hydrophilicity was studied by X-ray diffraction (XRD), atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS) and contact angle system, respectively, to examine the chemical composition of the film and the contact angle. The surface morphology of the semiconducting layer of organic pentacene was also investigated by using AFM and XRD, and confirmed that continuous crystalline film growth had occurred on the nc-TiO2 surface over flexible PI sheet. The semiconductor–dielectric interface of pentacene and nc-TiO2 films was characterized by current–voltage and capacitance–voltage measurements. This interface measurement in cross-link MIS structured device yielded a low leakage current density of 8.7×10−12Acm−2 at 0 to −5V, maximum capacitance of 102.3 pF at 1MHz and estimated dielectric constant value of 28.8. Furthermore, assessment of quality study of nc-TiO2 film in real-life flexibility tests for different types of bending settings with high durability (c.a. 30days) demonstrated a better comprehension of dielectric properties over flexible PI sheet. We expected them to have a keen interest in the scientific study, which could be an alternate opportunity to the excellent dielectric–semiconductor interface at economic and low temperature processing for large-area flexible field-effect transistors and sensors.

Photoexcited charge collection spectroscopy of two-dimensional polaronic states in polymer thin-film transistors

The polaronic structures associated with the interchain stacking in the polymer semiconductor bulk or polymer semiconductor-dielectric interface in fully operational thiophene-based thin-film transistors (TFTs) were investigated with a newly developed in situ photoexcited charge collection spectroscopy (PECCS). The in situ PECCS spectra of polymer semiconductors exhibited the \ensuremath{\pi}-\ensuremath{\pi}${}^{*}$ absorption peaks between 2.05 and 2.45 eV, which were well-matched with those in the Ultraviolet-visible (UV-vis) absorption spectra of the corresponding polymer films. The spectra also showed associated charge-induced absorption peaks at 1.32, 1.39, 1.58, and 1.71 eV below the \ensuremath{\pi}-\ensuremath{\pi}${}^{*}$ absorption edge. These charge-induced absorption peaks might be related to the delocalized polaron states located in the both polymer semiconductor bulk and semiconductor-dielectric interface of our polymer-based TFTs. From the spectral results, we were able to extract the polaronic density of states (DOS) of the polymer channel, and we confirmed that the denser interchain packing in the polymer semiconductor channel leads to a larger DOS near the band edge, resulting in higher field-effect mobility.

Enhanced Dielectric Properties of Ferroelectric Polymer Composites Induced by Metal-Semiconductor Zn-ZnO Core–Shell Structure

The effect of metal-semiconductor Zn-ZnO core-shell structure on dielectric properties of polyvinylidene fluoride (PVDF) composites was investigated. Zn-ZnO fillers were obtained by the heat-treatment of raw Zn particles under air. The enhanced dielectric constant of Zn-ZnO/PVDF composites results from the duplex interfacial polarizations induced by metal-semiconductor interface and semiconductor-insulator interface. The dielectric loss is still low because of the presence of ZnO semiconductor shell between Zn metal core and insulator PVDF matrix. Furthermore, the dielectric performance of as-prepared composites could be further optimized through adjusting the thickness of semiconductor shell.

Passivation of InP heterojunction bipolar transistors by strain controlled plasma assisted electron beam evaporated hafnium oxide

We present structural, stress, and electrical properties of plasma assisted e-beam evaporated hafnium dioxide (HfO2) layers on n-type InP substrates. These layers have subsequently been used for surface passivation of InGaAs/InP heterostructure bipolar transistors either alone or in combination with plasma enhanced chemical vapor deposited SiO2 layers. The use of stacked HfO2/SiO2 results in better interface quality with InGaAs/InP heterostructures, as illustrated by smaller leakage current and improved breakdown voltage. These improvements can be attributed to the reduced defect density and charge trapping at the dielectric-semiconductor interface. The deposition at room temperature makes these films suitable for sensitive devices.

Observation of ambipolar field-effect behavior in donor–acceptor conjugated copolymers

Although donor (D)–acceptor (A) conjugated copolymers possess an electron deficient unit, most D–A copolymers exhibit only hole transport properties (p-type). While there are some D–A copolymers that show ambipolarity, n-type behaviour is highly dependent on the type of acceptor used. In this work, ambipolar field-effect behaviour was derived from general D–A conjugated copolymers, believed to be a typical p-type material, by introducing a functional passivation layer between gate dielectric and active layers using polypropylene-co-1-butene (PPcB). The PPcB layer effectively covered the hydroxyl groups and induced a reduction in the energetic disorder at the semiconductor–insulator interface. As a result, the FET devices fabricated using D–A conjugated copolymers, such as PCDTBT, PTBT and Si-PCPDTBT, showed clear ambipolar properties.

Effects of gate dielectrics and their solvents on characteristics of solution-processed N-channel polymer field-effect transistors

In this study, we investigated the effects of polymer gate dielectrics and their solvents on the characteristics of n-channel top-gate-structured organic field-effect transistors (OFETs) that used poly{[N,N-9-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,59-(2,29-bithiophene)} (P(NDI2OD-T2)) (ActivInk™ N2200). The characteristics of P(NDI2OD-T2)-based OFETs are strongly dependent on the chemical properties of the polymer gate dielectrics used and the morphology of the semiconductor–dielectric interface, which is dependent of the dielectric solvent used for dielectric-layer deposition. Both spin-coated and inkjet-printed P(NDI2OD-T2)-based FETs exhibited reasonably high values of field-effect mobility (μFET) at 0.1–0.3 cm2 V−1 s−1 with poly(methyl methacrylate) as the gate dielectric and a number of carefully selected orthogonal solvents. The value of μFET decreased to 0.03 cm2 V−1 s−1 for a solvent with poor orthogonality (1,2-dichloroethane). This was due to the semiconductor–dielectric interface being rough owing to the dissolution and/or swelling of the underlying P(NDI2OD-T2) layer. In addition, the value of μFET decreased dramatically, to 0.005 cm2 V−1 s−1, with poly(4-vinyl phenol) (PVP) as the dielectric material, dissolved in a perfectly orthogonal solvent (1-butanol). This was due to electron trapping by the hydroxyl groups in PVP.

Supramolecular interaction facilitated small molecule films for organic field effect transistors

Metalloporphyrins and metal free porphyrins have been explored as active materials in field effect transistors. Amorphous forms of these porphyrins are preferred over their crystalline analogue due to the ease of solution processability. To achieve solution processability, a metalloporphyrin was anchored on a vinyl polymer by taking advantage of the supramolecular interaction between the metal and the pyridine moiety of the polymer. Non covalent bonding was preferred because it provides an opportunity to better manipulate the polymer's properties compared to its covalent bonding analogue. The binding between the porphyrin and the polymer was optimised in solution and the supramolecular complex was spun on various substrates to form thin films. The porphyrin was found to be uniformly distributed throughout the polymer films contrary to the existing approaches, wherein small molecule phase segregates in the polymer film. Field effect transistors were fabricated using the porphyrin-polymer complex and the device parameters were measured at atmospheric condition. The devices annealed at 80 °C showed hole carrier mobility of 2.0 × 10−4 cm2 V−1 s−1 with charge trapping at the dielectric semiconductor interface. Furthermore, the high carrier mobility observed at low temperature annealing makes this supramolecular complex an attractive candidate to explore in flexible substrates.