Semi-insulating Polycrystalline Silicon Research Articles

A fast-switching and ultra low-loss snapback-free reverse-conducting SOI-LIGBT with Adjustable Carrier Technology

A snapback-free Reverse-Conduction Silicon On Insulator Lateral Insulate Gate Bipolar Transistor (RC SOI-LIGBT) with Adjustable Carrier Technology (ACT LIGBT) is proposed in this paper. ACT LIGBT adds Semi-Insulating Polycrystalline Silicon (SIPOS) material on the extended gate dielectric, and introduces the potential of the surface SIPOS into the P-type drift region (P-Drift) through SiO2 trenches. ACT LIGBT generates the inversion layer of electrons in the P-Drift due to the linear potential distribution brought by the high resistance characteristic of SIPOS, resulting in the adjustment of the number of electrons and holes, and forming the technology of ACT. Additionally, ACT LIGBT adds a hole extraction path during it turned off. Meanwhile, compared to SSA LIGBT, ACT LIGBT optimized the BV (700V) by 34 %, while also optimizing the Von (1.69V) by 25 %, turn-off time (toff = 12ns) by 92 %, turn-off loss (Eoff = 0.69 mJ/cm2) by 79 %, and reverse recovery charge (Qrr = 32.98 μC/cm2) by 32.5 %, ultimately achieving a better compromise relationship among BV, Von, toff, Eoff, and Qrr.

Machine Learning-Based Figure of Merit Model of SIPOS Modulated Drift Region for U-MOSFET.

This paper presents a machine learning-based figure of merit model for superjunction (SJ) U-MOSFET (SSJ-UMOS) with a modulated drift region utilizing semi-insulating poly-crystalline silicon (SIPOS) pillars. This SJ drift region modulation is achieved through SIPOS pillars beneath the trench gate, focusing on optimizing the tradeoff between breakdown voltage (BV) and specific ON-resistance (RON,sp). This analytical model considers the effects of electric field modulation, charge-coupling, and majority carrier accumulation due to additional SIPOS pillars. Gaussian process regression is employed for the figure of merit (FOM = BV2/RON,sp) prediction and hyperparameter optimization, ensuring a reasonable and accurate model. A methodology is devised to determine the optimal BV-RON,sp tradeoff, surpassing the SJ silicon limit. The paper also delves into a discussion of optimal structural parameters for drift region, oxide thickness, and electric field modulation coefficients within the analytical model. The validity of the proposed model is robustly confirmed through comprehensive verification against TCAD simulation results.

Novel Si/SiC Heterojunction Lateral Double-Diffused Metal Oxide Semiconductor With SIPOS Field Plate by Simulation Study

A novel Si/SiC heterojunction Lateral Double-diffused Metal Oxide Semiconductor with the Semi-Insulating Polycrystalline Silicon field plate (SIPOS Si/SiC LDMOS) is proposed in this paper for the first time. The innovative terminal technology of Breakdown Point Transfer (BPT) had been applied on Si/SiC MOSFETs. This creative technology improved Breakdown Voltage (BV) of the proposed device, compared with the conventional Si LDMOS (Cov. LDMOS). In order to optimize the trade-off between BV and Specific On-Resistance (RON,SP), the SIPOS field plate is applied on Si/SiC LDMOS for the first time in this paper. At On-State, due to the internal electric field of SIPOS filed plate, the majority carriers accumulation layer is formed on the surface of the drift region for the proposed SIPOS Si/SiC LDMOS, which means RON,SP will be reduced. Meanwhile, the electric field modulation effect of SIPOS field plate can make the surface electric field distribute evenly, which leads to an increase of BV. In addition, due to the high-thermal conductivity of SiC substrate, the heat-dissipation efficiency of the proposed device is significantly improved. The simulation results show that the BV of SIPOS Si/SiC LDMOS is 428.4V, which increased by 78.4% in comparison with Cov. LDMOS (BV of 240.0V) with the same structure parameters. The R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,SP</sub> of SIPOS Si/SiC LDMOS is decreased from 33.2mΩ · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of Cov. LDMOS to 24.0mΩ · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , decreased by 27.7%. Furthermore, the figure-of-merit (FOM = BV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ) of SIPOS Si/SiC LDMOS reaches 7.6MW/cm2, which means SIPOS Si/SiC LDMOS has enough performance to break the Silicon limit.

Formation of Si nanocrystals in LP CVD semi-insulating polycrystalline silicon films

Influence of oxygen on silicon nanocrystals formation peculiarities and size in semi-insulating polycrystalline silicon thin films has been demonstrated by the means of local atomic surrounding sensitive electronic structure experimental studies. Low-pressure chemical deposition from the gas phase at a relatively low temperature leads to formation of semi-insulating polycrystalline silicon film containing nanocrystals with the grain size of 20–40 nm. At the same time, films oxygen doping result in formation of silicon nanocrystals arrays with the mean particle size less than 10 nm. Possibility of size-controlled Si nanocrystals formation followed by electronic structure reconstruction of amorphous films with nanocrystalline inclusions is discussed and can be found prospective for a range of possible applications.

Novel power U-MOSFET with SIPOS pillars

In this paper, a novel vertical U-MOSFET using Semi-Insulating Poly-crystalline Silicon pillars (SIPOS) is presented. The proposed SIPOS UMOS combines two benefits of majority carrier accumulation and electric field modulation to improve the trade-off between the breakdown voltage (BV) and the specific-on-resistance (Ron,sp) of the device. In the off-state, the reshaping effect of the SIPOS pillars enhances the vertical electric field strength and weakens the peak electric field at the bottom of the gate trench, thereby increasing the BV. In addition, a highly doped N-drift is allowed for SIPOS UMOS because of the enhanced depletion by the SIPOS pillars, leading to a low Ron,sp. In the on-state, the Ron,sp is further reduced by the majority carrier accumulation layer that formed in the drift region. The results carried by TCAD simulation show that the BV of SIPOS UMOS is increased by 12.5% and 36.2% compared with the conventional superjunction UMOS and the UMOS without the SIPOS pillars in the same drift length, respectively. Moreover, the Ron,sp of SIPOS UMOS is reduced by 31.3% and 85.8%, respectively.

Poly-Si(O)x passivating contacts for high-efficiency c-Si IBC solar cells

Highest conversion efficiency in crystalline silicon (c-Si) solar cells can be enabled by quenching minority carriers’ recombination at c-Si/contact interface owing to carrier-selective passivating contacts. With the semi-insulating poly-crystalline silicon (SIPOS, poly-Si) a very good passivation of c-Si surfaces was obtained. We have explored these passivating structures on IBC solar cells and obtained over 22% efficiency with over 23% within reach on the short term. We present in detail the passivation quality of p-type and n-type ion-implanted LPCVD poly-crystalline silicon (poly-Si) and its relation to the doping profile. Optimized poly-Si layers in the role of emitter and BSF showed excellent passivation (J0,emitter = 11.5 fA/cm2 and J0,BSF = 4.5 fA/cm2) and have been deployed in FSF-based IBC c-Si solar cells using a simple self-aligned patterning process. Applying an optimized passivation of FSF by PECVD a-Si:H/SiNx layer (J0,FSF = 6.5 fA/cm2) leads to a cell with efficiency of 22.1% (VOC = 709 mV, JSC = 40.7 mA/cm2, FF = 76.6%). Since over 83% FF has been reached with adjusted metallization technology on similar IBC structures, we believe 23% efficiency is within reach on the short term. Further improvement, especially at JSC level, is expected by deploying less absorbing carrier-selective passivating contacts based on poly-Si or wide bandgap poly-SiOx layers (J0 ~ 10 fA/cm2).

A Superjunction U-MOSFET With SIPOS Pillar Breaking Superjunction Silicon Limit by TCAD Simulation Study

A novel superjunction (SJ) vertical UMOSFET with semi-insulating POly-crystalline silicon pillar (SIPOS SJ-UMOS) is proposed and its mechanism is investigated by TCAD simulations. In the off-state, the reshape effect of SIPOS pillars enhances the vertical electric field strength and weakens the lateral field component, which increases the breakdown voltage (BV). In addition, the highly doped $N$ -pillars are allowed for the proposed device due to the enhanced depletion by the SIPOS pillars, which leads to a low specific ON resistance ( ${R}_{{\text {ON},\text {sp}}}$ ). In the on-state, an accumulation layer is formed in drift region leading to an additional reduction in the ${R}_{{\text {ON},\text {sp}}}$ . Simulation results show that the $\text {R}_{{\text {ON},\textit {sp}}}$ decreases 59%, and BV increases by 16.7%, simultaneously, breaking the SJ silicon limit, compared with those of a conventional SJ-UMOS with the same drift length. Moreover, the charge-imbalance endurance of SIPOS SJ-UMOS is also improved.

Simulation of 4H-SiC Trench Junction Barrier Schottky Diodes with High-k Dielectrics

In this paper, a novel 4H-SiC trench JBS (TkJBS) with high-k semi-insulating polycrystalline silicon (SIPOS) is proposed. By adopting a new high-k dielectrics-trench structure, the peak electric field at the corner of P+ region (COP) in Silicon Carbide (SiC) can be weakened significantly, and the device breakdown voltage can be enhanced significantly. SiC TkJBS has a 60.7% higher breakdown voltage (BV) and a 110.6% higher Baliga’s figure of merit (BFOM) than the conventional SiC JBSs, and the surface electric field (Esf) of the SiC TkJBS is 0.73 MV/cm lower than it at breakdown voltages, resulting in a much lower tunneling current (Ir). The reverse recovery characteristics of SiC TkJBS are also slightly better than those of the SiC JBS. It is indicated that SiC TkJBS is a promising candidate for next-generation high power diodes.

Design, Simulation, and Fabrication of 4H-SiC Power SBDs With SIPOS FP Structure

We introduce a field plate (FP) termination structure utilizing semi-insulating polycrystalline silicon (SIPOS) as the dielectrics in 4H-SiC Schottky barrier diodes (SBDs) in order to relieve the electric field enhancement at the junction corners and enhance the breakdown voltage of devices. In SIPOS FP structures, the maximum electric field $(E_{M})$ within the dielectrics can be significantly reduced in reverse blocking states due to the SIPOS with a higher dielectric constant $(k)$ . Simulation and fabrication of 4H-SiC SBDs with the novel and traditional SiO2 FP were carried out. The simulations were performed using the commercial 2-D device simulator DESSIS. Compared with a traditional SiO2 FP structure device, the optimal design of the new type of SIPOS FP structure will lead to an increase of 780 V in the breakdown voltage and a 44.8% $E_{M}$ reduction. From the experimental results, it has been proven that the new type of SIPOS FP structure indeed relieves the maximum electric field in the dielectric layer while simultaneously realizes an enhanced device breakdown voltage as high as 1630 V, which is about 74.5% of the ideal theoretical breakdown voltage.

Improved Planar MOS Barrier Schottky (PMBS) Rectifier with High-&lt;i&gt;k&lt;/i&gt; Dielectrics

In this paper, an improved planar MOS barrier Schottky (PMBS) rectifier is proposed which utilizes the PECVD deposited high-k semi-insulating polycrystalline silicon (SIPOS) as the MOS area gate dielectrics for the first time. By adopting the high-k SIPOS as the MOS gate dielectrics, the peak electric field at the interface betwwen dielectrics layer and SiC can be significantly relieved and the device reliability can obviously enhanced without considerable degradation of on-state characteristics. With the optimized the thickness of the SIPOS film, the breakdown voltage (BV) of 1500V for the fabricated device was achieved, which is approximately corresponds to 85% of the theoretical parallel plane breakdown voltage value calculated from the used epilayer structure. And the specific on-state resistance (RSP-ON) is about 4.2mΩ•cm2. The corresponding figure-of-merit of VB2/ RSP-ON for the proposed device is 535.7MW/cm2.

Carrier-selective contacts for Si solar cells

Carrier-selective contacts (i.e., minority carrier mirrors) are one of the last remaining obstacles to approaching the theoretical efficiency limit of silicon solar cells. In the 1980s, it was already demonstrated that n-type polysilicon and semi-insulating polycrystalline silicon emitters form carrier-selective emitters which enabled open-circuit voltages (Voc) of up to 720 mV. Albeit promising, to date a polysilicon emitter solar cell having a high fill factor (FF) has not been demonstrated yet. In this work, we report a polysilicon emitter related solar cell achieving both a high Voc = 694 mV and FF = 81%. The passivation mechanism of these so-called tunnel oxide passivated contacts will be outlined and the impact of TCO (transparent conductive oxide) deposition on the injection-dependent lifetime characteristic of the emitter as well as its implications on FF will be discussed. Finally, possible transport paths across the tunnel oxide barrier will be discussed and it will be shown that the passivating oxide layer does not lead to a relevant resistive loss and thus does not limit the solar cell's carrier transport. Contrary to amorphous silicon-based heterojunction solar cells, this structure also shows a good thermal stability and, thus, could be a very appealing option for next generation high-efficiency silicon solar cells.

4H-SiC Schottky barrier diodes with semi-insulating polycrystalline silicon field plate termination

Based on the theoretical analysis of the 4H-SiC Schottky-barrier diodes (SBDs) with field plate termination, 4H-SiC SBD with semi-insulating polycrystalline silicon (SIPOS) FP termination has been fabricated. The relative dielectric constant of the SIPOS dielectric first used in 4H-SiC devices is 10.4, which is much higher than that of the SiO2 dielectric, leading to benefitting the performance of devices. The breakdown voltage of the fabricated SBD could reach 1200 V at leakage current 20 μA, about 70% of the theoretical breakdown voltage. Meanwhile, both of the simulation and experimental results show that the length of the SIPOS FP termination is an important factor for structure design.

Design, Simulation, and Fabrication of Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) With New Termination Structure

In this paper, we introduce a new type of termination structure utilizing semi-insulating polycrystalline silicon (SIPOS) structures in conjunction with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> junction extension in order to reduce the area of termination device structure and increase the breakdown voltage. In SIPOS structures, one high-resistance layer is deposited between electrodes on two terminals such that the voltage between two electrodes is linearly distributed instead of the original nonlinear distribution. Compared to a traditional termination structure device (with a length of 180 μm and a breakdown voltage at 570 V), the optimal design of the new type of termination structure will lead to an increase of 40 V in the breakdown voltage and a 22.2% area reduction. From the perspective of device fabrication, it has been proven that the new type of termination structure indeed consumes less area while simultaneously realizing an enhanced device breakdown voltage as high as 710 V and a specific on-resistance at 137 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is consistent to the simulation results.

Low Specific on-Resistance Power MOS Transistor With Multilayer Carrier Accumulation Breaks the Limit Line of Silicon

In this paper, a new power metal-oxide-semiconductor field-effect transistor (MOSFET) with a FS surface to reduce the specific on-resistance <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> is proposed. Semi-insulating polycrystalline silicon (SIPOS) is deposited over a thin oxide layer. Drift-region concentration is higher in the proposed device than that of conventional lateral double-diffused MOS (LDMOS), and its structure with SIPOS is compared at the same breakdown voltage <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Bv</i> . In the proposed MOSFET, the effect of electric-field modulation is improved, when compared with an accumulation LDMOS transistor (ALDMOST) due to a complete 3-D reduced surface-field effect. An extra multilayer majority carrier is introduced on the sidewalls of the trench, which reduces <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> of the drift region. This indicates that the ideal silicon limit of the tradeoff of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Bv</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> has been broken due to the lowest <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> value in the proposed MOSFET. In the proposed MOSFET, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> (i.e., 13.5 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Bv</i> (i.e., 440 V) are improved greatly, when compared with the ALDMOST (i.e., with an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> of 26 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Bv</i> of 400 V) and a superjunction structure (i.e., with an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> of 98 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Bv</i> of 410 V).

Initial stage of semiinsulating polycrystalline silicon film growth

An experimental investigation is conducted into the initial stage of deposition for semiinsulating polycrystalline silicon (SIPOS) versus undoped polycrystalline silicon, with the N2O-to-SiH4 flow-rate ratios ranging from 0 to 0.23. It is shown that adding N2O to SiH4 does not change the pattern of the process. The initial stage is found to consist of a period of island growth followed by a period of coalescence, ending with the formation of a continuous film. Islands arise with a horizontal size of up to 95 nm. The minimum thickness of a continuous film is about 5 nm for SIPOS as against 22 ± 4 nm for undoped polycrystalline silicon.

An Analytical Model for Silicon-on-Insulator Reduced Surface Field Devices with Semi-Insulating Polycrystalline Silicon Shielding Layer

An analytical model is presented to determine the potential and electric field distribution along the semiconductor surface of new silicon-on-insulator (SOI) reduced surface field (RESURF) device. The SOI structure is characterized by a semi-insulating polycrystalline silicon (SIPOS) layer inserted between a silicon layer and a buried oxide. An improvement in the breakdown voltage due to the presence of the SIPOS shielding layer is demonstrated. Numerical simulations using medici are shown to support the analytical model.

Improving reliability of beveled power semiconductor devices passivated by SIPOS

Semi-insulating polycrystalline silicon films were prepared by direct current glow discharge on bevelled power semiconductor devices. Devices passivated by polyimide were also fabricated for comparison studies. The reverse current–voltage characteristic was studied at room temperature and high junction temperature. The differences arose from the remnant unbalance charges in the passivants as well as the varying dielectric strengths. Passivation materials applied to the beveled devices played a key role in achieving the targeted voltage. Results obtained indicated that the performance of power semiconductor devices passivated by SIPOS were superior to those passivated by polyimide, and SIPOS based process was effective and expected to enhance the reliability and yield.

Non-stoichiometric silicon oxide deposited at low gaseous N 2O/SiH 4 ratios

Semi-insulating polycrystalline silicon films were deposited using different N 2O/SiH 4 ratios, different pressures, at 650 and 700 °C, in a low-pressure chemical vapor deposition furnace. The deposition rate of the films increased with increasing pressure, increasing temperature and decreasing N 2O/SiH 4 ratio. At higher N 2O/SiH 4 ratios, more oxygen is incorporated in the film. Oxygen rich films had lower conductivities and lower dielectric constants than silicon rich films. The annealing of the films, at only 430 °C, decreased the conductivity indicating that more silicon-oxygen bonds are formed. The films also proved to be photoconductive.

Study of the chemical and structural organization of SIPOS films at the nanometer scale by TEM–EELS and XPS

Two films of semi-insulating polycrystalline silicon (SIPOS) have been prepared by low pressure chemical vapor deposition (LPCVD). Their physico-chemical properties are studied at the nanometer scale with transmission electron microscopy (TEM)–electron energy loss spectroscopy (EELS) and X-ray photoelectron spectroscopy (XPS) techniques by taking into account two main input parameters: the oxygen content and the condition of post-deposition anneal. The compositions of the films are SiO 0.17 and SiO 0.48. They are made of nanocrystalline silicon embedded in a SiO x matrix with different oxidation states of the silicon atoms. The less the films are oxygenated or the more the films are heat-treated, the more the fraction of crystallized silicon. This study provided a strong baseline to set up a process of fabrication for applications such as high voltage transistors.

Low-Pressure Chemical Vapor Deposition of Semi-Insulating Polycrystalline Silicon (SIPOS) and its Analysis: Application to Power Diode Passivation

Low-Pressure Chemical Vapor Deposition of Semi-Insulating Polycrystalline Silicon (SIPOS) and its Analysis: Application to Power Diode Passivation