Semi-floating Gate Transistor Research Articles

Photoelectric performance of InSe vdW semi-floating gate p–n junction transistor

Semi-floating gate transistors based on vdW materials are often used in memory and programmable logic applications. In this paper, we propose a semi-floating gate photoelectric p–n junction transistor structure which is stacked by InSe/h-BN/Gr. By modulating gate voltage, InSe can be presented as N-type and P-type respectively on different substrates, and then combined into p–n junction. Moreover, InSe/h-BN/Gr device can be switched freely between N-type resistance and p–n junction. The resistance value of InSe resistor and the photoelectric properties of the p–n junction are also sensitively modulated by laser. Under dark conditions, the rectification ratio of p–n junction can be as high as 107. After laser modulation, the device has a response up to 1.154 × 104 A W−1, a detection rate up to 5.238 × 1012 Jones, an external quantum efficiency of 5.435 × 106%, and a noise equivalent power as low as 1.262 × 10−16 W/Hz1/2. It lays a foundation for the development of high sensitivity and fast response rate tunable photoelectric p–n junction transistor.

Tactile tribotronic reconfigurable p-n junctions for artificial synapses

The emulation of biological synapses with learning and memory functions and versatile plasticity is significantly promising for neuromorphic computing systems. Here, a robust and continuously adjustable mechanoplastic semifloating-gate transistor is demonstrated based on an integrated graphene/hexagonal boron nitride/tungsten diselenide van der Waals heterostructure and a triboelectric nanogenerator (TENG). The working states (p-n junction or n+-n junction) can be manipulated and switched under the sophisticated modulation of triboelectric potential derived from mechanical actions, which is attributed to carriers trapping and detrapping in the graphene layer. Furthermore, a reconfigurable artificial synapse is constructed based on such mechanoplastic transistor that can simulate typical synaptic plasticity and implement dynamic control correlations in each response mode by further designing the amplitude and duration. The artificial synapse can work with ultra-low energy consumption at 74.2 fJ per synaptic event and the extended synaptic weights. Under the synergetic effect of the semifloating gate, the synaptic device can enable successive mechanical facilitation/depression, short-/long-term plasticity and learning-experience behavior, exhibiting the mechanical behavior derived synaptic plasticity. Such reconfigurable and mechanoplastic features provide an insight into the applications of energy-efficient and real-time interactive neuromodulation in the future artificial intelligent system beyond von Neumann architecture.

1T semi-floating gate image sensor with enhanced quantum efficiency and high response speed

The active pixel image sensor based on a semi-floating gate transistor (SFGT-APS) has been proposed and investigated; however, the quantum efficiency (QE) and the sensitivity are too poor to meet low illumination intensity and high-speed application due to the shallow junction of photodiodes. In this work, we demonstrate a new structure, called buried photodiode semi-floating gate transistor active pixel image sensor (BSFGT-APS), which possesses enhanced QE, high sensitivity, and fast response speed. Moreover, BSFGT-APS has the same fill factor with SFGT-APS, which is 55% with a 1 μm2 photodiode in 0.13 μm process. The basic device characteristics were investigated by Sentaurus TCAD simulation, including potential of photodiode, transient response, dark current, conversion gain, and full well capacity.

A Semi-Floating Gate Memory with Tensile Stress for Enhanced Performance

With the continuous scaling down of devices, traditional one-transistor one-capacitor dynamic random access memory (1T-1C DRAM) has encountered great challenges originated from the large-volume capacitor and high leakage current. A semi-floating gate transistor has been proposed as a capacitor-less memory with ultrafast speed and silicon-compatible technology. In this work, a U-shaped semi-floating gate memory with strain technology has been demonstrated through TCAD simulation. Ultra-high operation speed on a timescale of 5 ns at low operation voltages (≤ 2.0 V) has been obtained. And the tensile stress induced in its channel region by using contact etch stop layer (Si3N4 capper layer) was found to significantly improve the drain current by 12.07%. Furthermore, this device demonstrated a favorable retention performance with a retention time over 1 s, and its immunity to disturbance from bit-line has also been investigated that could maintain data under the continuous worst writing disturbance operation over 10 ms.

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications.

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

A Semi-Floating Gate Transistor with Enhanced Embedded Tunneling Field Effect Transistor

With the continuous semiconductor device scaling and the boosting of transistor density, it has become more and more important to design and realize novel paradigms of miniaturized electronic devices. A planar semi-floating gate transistor employs an embedded tunneling field-effect transistor for gate charging and discharging. U-shape semi-floating gate transistor uses a recessed trench to increase the channel length of the device. In this letter, we report the application of high- $k$ /metal gate in the transistor replacing the polysilicon control gate and SiO2 dielectric. The process and device characteristics have been theoretically studied and the simulation work has been carried out using Sentaurus TCAD tools. This transistor can be operated at lower voltages and higher writing, and erasing operation speed has been achieved. The device power consumption has been successfully reduced.

Analysis and modeling of the semi-floating transistor based 1T pixel in CMOS image sensors

A semi-floating gate transistor (SFGT) based 1T pixel can achieve the same functions as the traditional 3T active pixel sensor (APS). The SFGT APS improves the fill factor and the pixel density of CMOS image sensors to meet the requirement for high sensitivity application. This paper proposes an equivalent circuit model for the SFGT APS. The model shows that the intrinsic capacitances and the applied voltages affect the SFG voltage range, the maximum non-saturated light power, the conversion gain and the full well capacity (FWC). The simulation results are obtained by technology computer aided design (TCAD), which shows a good agreement with theoretical calculation. A higher drain voltage improves the output swing, the maximum non-saturated light power, the conversion gain and the FWC. A lower capacitance CPIP increases the output level and the conversion gain at the expense of the light range and the FWC. The model also proposes optimization for better pixel design.

Investigation of Dynamic Threshold Voltage Behavior in Semi-Floating Gate Transistor for Normally-Off AlGaN/GaN HEMT

In this paper, an inverter composed of semi-floating gate (SFG) transistor and a load resistor was analyzed. Varying threshold voltage $(V_{\mathrm {th}})$ during switching was observed. This dynamic $V_{\mathrm {th}}$ behavior of SFG device is because of the special device structure of SFG transistors. Based on the $V_{\mathrm {th}}$ -programmable behavior of the SFG transistor, a SFG-based GaN high electron mobility transistor was proposed and enhancement-mode was realized with writing-0 into the transistor during every switching operation by simulation.

Investigation of Temperature Dependence, Device Scalability, and Modeling of Semifloating-Gate Transistor Memory Cell

A semifloating-gate transistor had been proposed and its memory function has been demonstrated recently. In this paper, we further investigate its temperature dependency, device scalability, and device modeling. The high-temperature behavior is studied by measuring its endurance, retention, and disturbance immunity at 85 °C. The device scalability down to the 14-nm technology node is investigated by simulation. Its macrodevice model for circuit design is also developed. Finally, a memory array with the specific peripheral circuits is designed using the device model developed in this paper.

Characterization and Optimization of a Single-Transistor Active Pixel Image Sensor with Floating Junction Connected to Floating Gate

The application of semifloating gate transistor (SFGT) as the single-transistor active pixel image sensor (APS) is investigated in this paper. This single-transistor (1T) APS can realize the functions of the conventional 3T CMOS image sensor. The device operation mechanism, optimization methods, and transient behavior measurements will be discussed. Because the floating junction of this device is connected to the floating gate, special behaviors such as floating gate voltage pinning effects were observed. The transient time measurement emulating the exposure procedure also confirmed the light sensing function as a single-transistor image sensor.

A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation

As the semiconductor devices of integrated circuits approach the physical limitations of scaling, alternative transistor and memory designs are needed to achieve improvements in speed, density, and power consumption. We report on a transistor that uses an embedded tunneling field-effect transistor for charging and discharging the semi-floating gate. This transistor operates at low voltages (≤2.0 volts), with a large threshold voltage window of 3.1 volts, and can achieve ultra-high-speed writing operations (on time scales of ~1 nanosecond). A linear dependence of drain current on light intensity was observed when the transistor was exposed to light, so possible applications include image sensing with high density and performance.