Semiconductor Vendors Research Articles

Performance Analysis of Secure Elements for IoT

New protocol stacks provide wireless IPv6 connectivity down to low power embedded IoT devices. From a security point of view, this leads to high exposure of such IoT devices. Consequently, even though they are highly resource-constrained, these IoT devices need to fulfil similar security requirements as conventional computers. The challenge is to leverage well-known cybersecurity techniques for such devices without dramatically increasing power consumption (and therefore reducing battery lifetime) or the cost regarding memory sizes and required processor performance. Various semiconductor vendors have introduced dedicated hardware devices, so-called secure elements that address these cryptographic challenges. Secure elements provide tamper-resistant memory and hardware-accelerated cryptographic computation support. Moreover, they can be used for mutual authentication with peers, ensuring data integrity and confidentiality, and various other security-related use cases. Nevertheless, publicly available performance figures on energy consumption and execution times are scarce. This paper introduces the concept of secure elements and provides a measurement setup for selected individual cryptographic primitives and a Datagram Transport Layer Security (DTLS) handshake over secure Constrained Application Protocol (CoAPs) in a realistic use case. Consequently, the paper presents quantitative results for the performance of five secure elements. Based on these results, we discuss the characteristics of the individual secure elements and supply developers with the information needed to select a suitable secure element for a specific application.

Assessment of Competitive Edge of Major Global Semiconductor Vendors for Self-Driving Solutions (Level 3 and Above)- Evaluation of Qualcomm, Intel, and Nvidia

Assessment of Competitive Edge of Major Global Semiconductor Vendors for Self-Driving Solutions (Level 3 and Above)- Evaluation of Qualcomm, Intel, and Nvidia

Interview

interview

Modeling and Evaluating the Gate Length Dependence of BTI

Bias temperature instability (BTI) is a major reliability concern in the current and upcoming technologies. Current mitigation techniques mainly target circuit and system levels through reducing the stimuli that govern BTI. Such mitigation techniques typically come with non-negligible overheads, which might not be acceptable—especially in smaller technology nodes where the available design margins are tighter. Semiconductor vendors report different BTI degradations in their technology and hence circuit designers need to consider such technology features when designing for reliability. Recently, TSMC reported that BTI strongly depends on the gate length ( ${L}$ ) of transistors in their 10nm technology node. In this brief, we are the first to investigate the role that gate length dependence of BTI may play as a new degree of freedom in the design for reliability. Based on the reported data from TSMC, we propose to incorporate the gate length dependency into a state-of-the-art physics-based BTI model. Then, we propose a new method of transistor stacking that optimizes circuits (e.g., SRAM cells) with respect to on/off current ratios in which ${L}$ -dependency of BTI is taken into account. Compared to state of the art, our approach results in BTI-hardened SRAM cells with 50% better on/off current ratio along with $3\times$ better reliability at the cost of a 20% area overhead.

New Worst-Case Timing for Standard Cells Under Aging Effects

The design of reliable circuits in current semiconductor technologies requires worst-case estimations of degradation effects during chip signoff. Hence, semiconductor vendors provide worst-case cell delays in the form of slow/slow process corners and best-case cell delays in fast/fast process corners. By providing these corner cases, EDA signoff tools can accurately estimate the circuit timing in which a reliable operation (i.e., no timing violations) is guaranteed for the projected lifetime. State of the art assumes that a standard cell exhibits the worst-case delay increase when all of its transistors uniformly exhibit worst-case aging-induced degradation. As our first contribution, we are the first to demonstrate that this assumption is incorrect and leads to a considerable underestimation of up to 55% in circuit timing. To find the worst-case cell delay, instead of searching across all combinations of non-uniform transistor degradations, we propose reducing the search space by exploiting circuit topology, that is, using cell input vectors to determine transistor duty cycles. Our aim is to find the worst-case input vectors of a cell, which lead to the highest possible shift in rise and fall propagation delay for each standard cell. Since the number of inputs of a standard cell is significantly smaller than its number of transistors, exploring this reduced search space becomes feasible. We show how considering a uniform worst-case degradation for each transistor underestimates the actual degradation in standard cells. In fact, actual non-uniform worst-case inputs vectors result in 83% higher standard cell delay on average (compared to applying peak degradation uniformly) with a peak of $60\boldsymbol \times $ for an inverter under a high load capacitance.

Quick Prototyping Design for More than Moore era

[Background and Motivation] System in Package (SiP) is pulling the evolution of technology instead of deep submicron of LSI. SiP assists coming AI/IoT/5G world. SiP has many implementation variations. When we examine the chip and package implementation technique for the target product, it's important task to find the optimal solution for the product considering trade-off between cost and performance. Compared with mass production products, it's important to optimize costs especially for small volume production products. Moreover, in terms of performance, compared to conventional packages, for high frequency products and SiP, since the margin becomes small and confirming system level electrical characteristics are necessary, in addition to conventional conceptual design and detail design, prototyping design is required to test its electrical characteristics while keeping lower cost. [Technical callenge] To do prototyping design at the early stage of product and find the optimum solution of the product, we created short turn-around time(TAT) iteration environment and distributed prototyping design. Quick Prototyping, which is a short TAT iteration environment, is based on the LSI/Package/PCB integrated co-design environment, estimates the chip size from the signal number of product, performs LSI design prototyping, using package automatic net assignment and the substrate auto routing, proceeds package prototype design and then confirms electrical characteristics. In the above, itfs possible to consider multiple implementation variations. In the distribution of prototype design, we utilize the LPB format (IEC 63055/IEEE 2401), have eliminated the interface(I/F) barriers between companies and tools, and have developed an environment for design prototypes and checking their characteristics throughout the industry. [Results and Conclusions] In collaboration with Semiconductor vendor Socionext Inc., as the above benchmark, 3D Flip Chip-Chip Scale Package(FCCSP) (with memory package with Package on Package(PoP) method) and 3D Fan-Out Wafer Level Package(FOWLP) (similarly in PoP method) as samples, the prototype design was created out. By comparison of the electrical characteristics, the Self Inductance of the FOWLP becomes half or less than FCCSP, the power supply noise could be suppressed. The shielding effect of FOWLP reduced the influence of crosstalk. We confirmed that FOWLP has advantage of electrical characteristics. On the cost side, in the LSI implementation of the FOWLP side, only the function blocks requiring performance were replaced with the fine node by chip partitioning, we examined to suppress the increase in cost while maintaining the performance advantage of FOWLP. With Quick Prototyping, cost and performance balance can be examined in the product review early stages, also by utilizing the LPB format for Quick Prototyping, from the negotiation stage with business partners, we can share the design data, focus on tuning the product itself and improve the competitive SiP products.

Overview of Device-to-Device Communication and Vehicle-to-Vehicle Communication

5G (5th generation mobile networks or 5th generation wireless systems) is the next major phase of mobile telecommunications standards beyond the current 4G LTE (Long-Term Evolution) standards. 5G technology needs to be specified, developed, and deployed by a variety of industry players including network equipment vendors, network operators, semiconductor vendors, and device manufacturers. The scope of 5G will range from mobile phones to next-generation automobiles. Device to Device (D2D) Communication is regarded as a promising technology in 5G to provide low power, high data rate and low latency. Introducing D2D poses many challenges and risks to the longstanding cellular architecture, which is centred on the base station.

Hardware Acceleration

It is an exciting era for hardware acceleration. Lack of device scaling for general-purpose processors has motivated the need for hardware specialization in virtually every computing system, from mobile processors to desktops to data centers. As a result, almost all major semiconductor vendors and cloud service providers have chips that include accelerators, large or small, for a variety of applications. In addition, electronicdesign- automation vendors are introducing new high-level synthesis tools to lower the design barriers to acceleration.

Security Assurance Guidance for Third-Party IP

System OEMs are increasingly adopting the motto “Trust but verify” when it comes to their supply chains. After several public incidents in which trusted vendors unknowingly provided vulnerable components, OEMs are requesting evidence of security assurance before integrating components into their products. It can be problematic for semiconductor vendors to provide such evidence since their products often contain 3 rd party components that are typically treated as black boxes. Moreover, asking 3 rd party vendors to provide such evidence for their components is equally problematic due to the many integration unknowns and a lack of applicable literature on security assurance for standalone technologies. We address these issues by defining a security process and relationship between semiconductor vendors and trusted 3 rd party component providers and a practical methodology to produce standardized quality security assurance evidence. We provide example applications of the methodology using several open source components.

Secure split test techniques to prevent IC piracy for IoT devices

Globalization of semiconductor manufacturing and related activities has led to several security issues like counterfeiting, IP infringement and cloning etc. Counterfeiting not only affects the business and reputation of semiconductor vendor, it will affect the reliability of critical applications. Internet of Things (IoT's) is an emerging application area for semiconductors in which security is a prime concern. Identity or authentication of a device in the network of millions of devices in IoT's is very important. In this paper, we present Secure Split Test with functional testing capability (SSTF) scheme to mitigate the counterfeits coming out from untrusted foundries. The SSTF is suitable for low cost/low end devices. To address the identity management issue in IoT's and counterfeiting of ICs, a Physical Unclonable Function based SSTF (PUF-SSTF) is presented. PUF-SSTF is suitable for ICs targeted to use in smart phones and IoT ‘s. PUF-SSTF is a security solution to address: mitigating the counterfeit ICs coming out from untrusted foundries, identity management in IoT's and licensing the device features, which will benefit the fabless semiconductor vendors for licensing and entitlement management. The proposed SSTF and PUF-SSTF techniques are implemented in both ASIC and FPGA and security analysis is performed. The security analysis results are in par with earlier secure split test techniques like Connecticut Secure Split Test (CSST). The proposed techniques will create the comprehensive secure supply chain solution, which will benefit fabless semiconductor vendor and end-user.

Processing of an Integrated Optical Sensor with Almost 100% Quantum Efficiency

We report on a new fabrication process of integrated PIN photodetectors with very high quantum efficiencies into a 0.35μm CMOS process, including improved processing for bottom antireflective coating (BARC). The integration process is such that complete modularity of the CMOS process remains untouched by the implementation of the highly efficient photodetectors. Due to the fact that only two additional masks and one ion implantation step are necessary for the implementation of PIN photodetectors including BARC, this integration process also proves to be very cost effective. In-house processed p-doped intrinsic layers with EPI doping levels as low as 1∙1012/cm3 serve as CMOS base material. This is a doping level that major semiconductor vendors could not provide. With just one additional mask and ion implantation we provide doping concentrations very similar to standard CMOS substrates to areas outside the photoactive regions. Thus full functionality of the standard CMOS logic can be guaranteed while the photodetectors highly benefit from the low doping concentrations of the intrinsic EPI. Special surface protection techniques are performed to maintain the low doping concentrations of the substrate during the complete CMOS processing. To further enhance the photosensor’s quantum efficiency especially of photodetector arrays we present a new BARC process. With this new BARC process we can lower the dark current in photodiode arrays by at least one order of magnitude compared to currently established plasma-etch methods. The following photodiode parameters could be accomplished for 100x100μm2 single photodiodes with BARC: quantum efficiencies of 76%, 99.8% and 74% at wavelengths of 500nm, 675nm and 850nm, respectively, capacitances of 0.13pF and dark currents of 1.18pA for unbiased photodiodes.

The Efforts of Japanese Semiconductor Vendors toward Standardization of the Automotive LAN Bus-system:

The Efforts of Japanese Semiconductor Vendors toward Standardization of the Automotive LAN Bus-system:

Design of FlexRay Communication Network Using Active Star

FlexRay is a new standard of network communication system which has been developed for future automotive applications. It was devised by automotive manufacturers and semiconductor vendors. FlexRay provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for automotive applications. In this paper, FlexRay system is first designed using SDL (Specification and Description Language). For hardware implementation, FlexRay system is designed using Verilog HDL based on the SDL design result. The disigned system is synthesized using Synopsys Design Compiler with the Hynix 0.18 ?m cell library. For constructing a FlexRay communication network, the active is used since active star systems can provide high speed data transmission up to 10 Mbps. The performance of the active star network is tested using one transmitter node and two receiver nodes.

Tree bitmap

Even with the significant focus on IP address lookup in the published literature as well as focus on this market by commercial semiconductor vendors, there is still a challenge for router architects to find solutions that simultaneously meet 3 criteria: scaling in terms of lookup speeds as well as table sizes, the ability to perform high speed updates, and the ability to fit into the overall memory architecture of an Level 3 forwarding engine or packet processor with low systems cost overhead. In this paper, we describe a scheme that meets all three criteria. By contrast, published and commercial semiconductor solutions meet some but not all of these three criteria.For example, many approaches that provide dense tables have poor update times; others require large amounts of expensive high speed memory dedicated to this application. Many IP address lookup approaches do not take into account the flexibility of ASICs or the structure of modern high speed memory technologies such as RLDRAM[1] and FCRAM[2]. In this paper, we present a family of IP lookup schemes using a data structure that compactly encodes large prefix tables in order to address the criteria listed above. We also present a series of optimizations to the core algorithm that allows the memory access width of the algorithm to be reduced at the cost of memory references or allocated memory. Such flexibility in performance versus density is an important feature for the lookup engine of routers that may be deployed in different networks with varying requirements on address lookup length and table density (e.g. global IPv4 networks, global v6, VPN based v4 networks, MPLS, and IP tunneling encapsulation points).

Standards - Switch fabric interfaces

Switch fabrics are fundamental building blocks in a wide range of communication platforms. However, despite the growing need for next-generation switches and routers, semiconductor vendors have been slow to develop switch fabric chipsets. In addition to the many technical challenges associated with the deployment of such fabrics, industry analysts agree that a key factor impeding wide-scale exploitation is a lack of standardization in interconnecting fabric components. Many of the more than 30 companies that develop switch fabrics offer excellent price and performance, but none guarantee compatibility with other vendor offerings or even with future generations of their own products. The market consists of several point solutions with no reliable and coherent roadmap. In these uncertain times, assurance of supply is a major issue in selecting a silicon vendor. Standard interfaces will make it possible to replace a discontinued device without requiring a new system design. The guaranteed availability of backup products will reduce the risks associated with each device and let systems designers select newer and more cutting-edge offerings.

Gemplus and Schlumberger increase dominance

Gemplus and Schlumberger account for two in three chip cards shipped worldwide, according to the latest analysis of the smart card industry from Gartner Dataquest * * Worldwide Chip Card Market Share, 2000: Card Vendors and Semi-conductor Vendors, Gartner Dataquest, Tel: +44 1784 268819I.

Interconnection Challenges of the 1990'8

ABSTRACTSilicon device performance has improved dramatically over the past two decades. During that time, the portion of total circuit delay attributable to interconnect wiring has increased to nearly half. Changes in the use of aluminum wiring and silicon oxide insulators must be considered to further improve performance.The generation of ULSI circuitry now under development in the industry depends heavily on innovations in materials and processes to achieve significant improvements in wiring density and circuit performance. The subsequent generation places even greater demands on materials improvements for lower resistivity wiring and a lower dielectric constant insulator. Integrating materials and methods compatible with semiconductor processing while ensuring device reliability will create a significant financial challenge in addition to the technical challenge.This presentation enumerates the interconnection challenges facing the materials scientist and the circuit designer. The ultimate limits in materials improvements are predictable and finite. Further improvements will be derived from design innovations such as treating interconnects as active rather than passive devices. Accurate physical modelling of MLM structures will complement even more complex electrical modelling. Manufacturing sciences will grow in sophistication if implementation is to succeed. The financial burden of these technical challenges will foster collaborations among semiconductor manufacturers, equipment vendors, and research universities.

Polystrate and Ultrastrate: Complementary Multichip Module Technologies

CMOS devices are approaching the 50 MHz threshold at which conventional electronic assemblies—based on packaged components (SMD, PGA, etc.) mounted on high‐density printed circuit boards—impose a serious penalty on the speed of the raw die provided by the semiconductor vendors. To improve the packaging density and to reduce the resistive and capacitive loads as well as signal delays at the second level of interconnection, new packaging concepts for VLSI and ULSI components are imperative. Multichip modules (MCM) seem to be the only adequate solution to the interconnect problem. Ultrastrate—the author's company's MCM technology with multilayer thin‐film build‐ups—is briefly presented. Life cycles for products in the electronics industry are becoming ever shorter. Electronics engineers must package more complicated circuits in smaller volumes and in a shorter time. On the other hand, prototyping an MCM from the electrical schematic takes at least 12 weeks. There is as yet no equivalent of a PCB breadboard for MCMs! In response to this situation, Polystrate is a new process which has been developed to provide a flexible and fast prototyping tool for MCMs. It satisfies the most stringent requirements with regard to performance, economics and ease of modification, and offers a very fast turn‐around time. The technological synergies between Ultrastrate and Polystrate allow for a smooth transition between the prototyping and production phases.

A user's view of the new MIL-STD-883 procedure 5012

The MIL-STD-883 Procedure 5012, Fault Coverage Measurement for Digital Microcircuits, is reviewed. Procedure 5012 specifies a standard fault set and fault coverage calculation techniques. The motivation and benefits of the standard are detailed. The effect of the standard fault set is studied by analysis and presentation of test case data. An actual example illustrates the costs of generating a compliant fault coverage report. US Department of Defense contractors, fault simulation developers, and semiconductor vendors are encouraged to create the necessary supporting infrastructure for the new standard. >

Semiconductor vendors paying closer attention to ASIC : JEE (Japan) 27 (February 1990)

Semiconductor vendors paying closer attention to ASIC : JEE (Japan) 27 (February 1990)