Self-heating Research Articles

Analysis of Self-Heating Effect in Graded-Channel Silicon-on-Insulator nMOSFETs

This paper presents a Self-Heating (SH) analysis using conventional Silicon-On-Insulator (SOI) in comparison to Graded- Channel (GC) SOI nMOSFETs devices. The analysis is performed comparing devices with the same mask channel length and with the same effective channel length. Two-dimensional numerical simulations are performed in both studies considering the lattice heating. The models and the thermal conductive constant used in these simulations are also presented. It is demonstrated that GC devices with the same mask channel length presents similar occurrence of SH independently of the length of lightly doped region despite the larger drain current. On the other hand, for similar effective channel length, the SH is less pronounced in GC transistors as the mask channel length has to be increased in order to compensate the current difference.

HCI Lifetime Correction Based on Self-Heating Characterization for SOI Technology

Self-heating (SH) effects, which were observed during the development of silicon-on-insulator (SOI) technology for high-performance circuits, raise questions concerning the validity of the extrapolation method used for hot carrier injection (HCI). In this paper, we propose a new methodology for lifetime prediction based on DC HCI stress for SOI technology. The SH is quantified using coupled DC HCI stress and gate resistance measurements for different transistor widths. Then, the degradation part due to SH is removed, enabling accurate HCI lifetime prediction when SH effects are present.

Degradation Behaviors of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors Under DC Bias Stresses

Device degradation behaviors of typical-sized n-type metal-induced laterally crystallized polycrystalline silicon thin-film transistors were investigated in detail under two kinds of dc bias stresses: hot-carrier (HC) stress and self-heating (SH) stress. Under HC stress, device degradation is the consequence of HC induced defect generation locally at the drain side. Under a unified model that postulates, the establishment of a potential barrier at the drain side due to carrier transport near trap states, device degradation behavior such as asymmetric on current recovery and threshold voltage degradation can be understood. Under SH stress, a general degradation in subthreshold characteristic was observed. Device degradation is the consequence of deep state generation along the entire channel. Device degradation behaviors were compared in low Vd-stress and in high Vd-stress condition. Defect generation distribution along the channel appears to be different in two cases. In both cases of SH degradation, asymmetric on current recovery was observed. This observation, when in low Vd-stress condition, is tentatively explained by dehydrogenation (hydrogenation) effect at the drain (source) side during stress

A physically based compact model of partially depleted SOI MOSFETs for analog circuit simulation

In this paper, the Southampton Thermal AnaloGue (STAG) compact model for partially depleted (PD) silicon-on-insulator (SOI) MOSFETs is presented. The model uses a single expression to model the channel current, thereby ensuring continuous transition between all operating regions. Furthermore, care has been taken to ensure that this expression is also infinitely differentiable, resulting in smooth and continuous conductances and capacitances as well as higher order derivatives. Floating-body effects, which are particular to PD SOI and which are of concern to analog circuit designers in this technology, are well modeled. Small geometry effects such as channel length modulation (CLM), drain-induced barrier lowering (DIBL), charge sharing, and high field mobility effects have also been included. Self-heating (SH) effects are much more apparent in SOI devices than in equivalent bulk devices. These have been modeled in a consistent manner, and the implementation in SPICE3f5 gives the user an additional thermal node which allows internal device temperature rises to be monitored and also accommodates the modeling of coupled heating between separate devices. The model has been successfully used to simulate a variety of circuits which commonly cause problems with convergence. Due to its inherent robustness, the model can normally achieve convergence without recourse to the setting of initial nodal voltage estimates.

Experimental determination of self-heating in submicrometer MOS transistors operated in a liquid-helium ambient

Self-heating (SH) in submicrometer CMOS transistors operated at liquid-helium temperature and under different bias conditions was experimentally verified by measuring the temperature T/sub Si/ in the proximity of the device. T/sub Si/ was measured by using a silicon resistor, placed in the same bulk nearby the device under test, as a temperature sensor. It was found that the heat generated by the NMOS transistor of a CMOS inverter structure penetrates deep into the substrate and reduces very strongly the n-well impedance, giving rise to large variations in the kink of the I/sub drain/-V/sub drain/ characteristics of the neighbor PMOS transistor. Experimental results confirm that SH must not be underestimated when characterizing and modeling low-temperature device operation. >