Self-checking Logic Research Articles

Multi-bits error detection and fast recovery in RISC cores

The particles-induced soft errors are a major threat to the reliability of microprocessors. Even worse, multi-bits upsets (MBUs) are ever-increased due to the rapidly shrinking feature size of the IC on a chip. Several architecture-level mechanisms have been proposed to protect microprocessors from soft errors, such as dual and triple modular redundancies (DMR and TMR). However, most of them are inefficient to combat the growing multi-bits errors or cannot well balance the critical paths delay, area and power penalty. This paper proposes a novel architecture, self-recovery dual-pipeline (SRDP), to effectively provide soft error detection and recovery with low cost for general RISC structures. We focus on the following three aspects. First, an advanced DMR pipeline is devised to detect soft error, especially MBU. Second, SEU/MBU errors can be located by enhancing self-checking logic into pipelines stage registers. Third, a recovery scheme is proposed with a recovery cost of 1 or 5 clock cycles. Our evaluation of a prototype implementation exhibits that the SRDP can successfully detect particle-induced soft errors up to 100% and recovery is nearly 95%, the other 5% will inter a specific trap.

FPGA Implementation of Self-Testing Logic Gates, Adders and Multipliers

This study presents self-checking designs for arithmetic and logic circuits using Field Programmable Gate Array (FPGA) design. At present, we are implementing every circuit using VLSI technology because of its excellent features like low power, less area, wide implementation. Since finding error manually is a tedious process, self-checking method would be most wanted. Self-checking circuits are preferable to Automatic Testing Equipment (ATE) because they demand less hardware, low cost and takes very less test application time. The replica construction and pattern recognition are the two methods presented for self-checking logic gates. Self-checking single-bit full adder, 4-bit adder and 2-bit multiplier circuits are implemented and tested on EP2C20F484C7 Altera Cyclone-II FPGA device using Very High-Speed Integrated Circuits Hardware Description Language (VHDL) script. The test data input samples are applied through input switches and the Error/No Error results are obtained on the 7-segment display device. This study discuss in detail about basic self-checking methods with a experimental way. If the complexity of the circuit increases, the components used and the number of connections between the components increases. As a result, the probability of error occurrence increases for complex designs. But this error occurrence can be avoided to the maximum by using self-checking circuits at different build stages in the complex circuit model. The reliability of any system becomes very important especially in the area of applications such space technology, medical image analysis, military communications, etc.

INCORPORATING FAULT-TOLERANT FEATURES IN VLIW PROCESSORS

In recent years, very long instruction word (VLIW) processor has attracted much attention in that it offers a high instruction level parallelism and reduces the hardware design complexity. In this paper, we present two fault-tolerant schemes for VLIW processors. The first one is termed as test-instruction scheme which is based on the concept of instruction duplication to detect the errors. The process of test-instruction scheme consists of the error detection, error rollback recovery and reconfiguration. The second approach is called self-checking scheme which adopts the concept of self-checking logic to detect the errors. A real-time error recovery procedure is developed to conquer the errors. We implement the proposed designs of fault-tolerant VLIW processor in VHDL and employ the fault injection and fault simulation to validate our schemes. The main contribution of this research is to present the complete frameworks from error detection to error recovery for fault-tolerant design of VLIW processors. Experience learned from this investigation is that the issues of error detection and error recovery entail considering together. Without taking both issues into account simultaneously, the outcomes may lead to the improper conclusions.

Self-checking logic design for FPGA implementation

Field programmable gate arrays (FPGAs) are being increasingly used in many systems including intelligent instrumentation. A synthesis algorithm for generating self-checking combinational logic for implementation on look-up table based FPGAs is presented. The algorithm maps Boolean functions into FPGAs such that self-checking features are automatically incorporated into designs, allowing on-line detection of faults in the combinational function block within any configurable logic block of an FPGA and on the interconnect lines that connect these blocks. This is accomplished by utilizing two types of cells, a functional cell and a checker cell, that generate complementary outputs during normal operation, and outputs of the same value in the presence of a fault. If a fault occurs in any intermediate functional cell, it is automatically propagated to the primary outputs. A checker cell is then used to verify the correctness of the final outputs, thus allowing self-checking.

Fault-tolerant computing: fundamental concepts

The basic concepts of fault-tolerant computing are reviewed, focusing on hardware. Failures, faults, and errors in digital systems are examined, and measures of dependability, which dictate and evaluate fault-tolerance strategies for different classes of applications, are defined. The elements of fault-tolerance strategies are identified, and various strategies are reviewed. They are: error detection, masking, and correction; error detection and correction codes; self-checking logic; module replication for error detection and masking; protocol and timing checks; fault containment; reconfiguration and repair; and system recovery.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design methodology and microdiagnostics development for a self-checking microprocessor

The conventional design of electronic circuits is intolerant to operational faults. Self-checking logic is aimed at online fault detection and can hence be incorporated to achieve reliable operation. In this paper, the design of a self-checking microprocessor is discussed. Self-checking strategies for different functional units are selectively and judiciously applied, and also modified wherever necessary, for the design of the register section, the arithmetic &amp; logic unit and the control unit. A self-checking microprogrammed control unit, capable of supporting normal instruction execution concurrently with diagnostics, is developed. The design methodology has been applied to Intel's 8085A microprocessor as a case study to make it self-testing. Overheads involved have also been estimated.

Self-checking logic arrays

Self-checking blocks may be used to ensure concurrent error detection in integrated circuits. On the other hand, logic arrays such as PLAs, ROMs and RAMs are essential to circumvent the increasing complexity of VLSI circuits. Efficient self-checking schemes for logic arrays are therefore essential for concurrent error detection in VLSI circuits. The paper describes schemes that incur low area overhead.

On Separable Unordered Codes

Unordered codes have proven useful for designing failsafe, fault-secure, and self-checking logic circuits. In many applications it may be desirable to have separate information bits and check bits, i.e., a separable code. This correspondence gives a procedure for adding check bits to a set of information k-tuples to produce an unordered code. The general case where not all 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> possible k-tuples are used is considered. For an arbitrary set of k-tuples, the minimum number of check bits is shown.

Self-checking binary logic systems using ternary logic circuits

The present status of multivalued logic is highlighted in a Canadian context. A particular example is given of the use of ternary circuits in the solution of the problem of testability of binary logic, through the introduction of a new concept called 2-of-3-valued logic. Its application to the design of combinational and sequential self-checking systems is demonstrated. Topics discussed include: multivalued logic, testability, reliability, ternary logic, CMOS logic, and fault tolerance.

The 3B20D Processor &amp; DMERT Operating System: 3B20D Central Processing Unit

The 3B20D Processor has been developed to meet the need for very reliable, real-time control of a variety of Bell System applications. To achieve its high-reliability goals, most of the major subsystems within the processor are duplicated, including the Central Processing Unit (CPU). The CPU uses a 32-bit architecture throughout, including the memory and input/output buses. Extensive self-checking logic is employed. The 3B20D CPU is microprogrammed to select dynamically up to four instruction sets. The microstore uses a 64-bit word with up to 16K words of high-speed bipolar PROM or RAM available. This rich emulation capability makes the 3B20D Processor ideal for emulating existing instruction sets and porting existing software. Peripheral units are connected to the CPU via the Direct Memory Access unit (DMA). The DMA controllers provide direct memory transfers between the main store and peripheral devices, reducing the load placed on the central control to process input/output requests.

Designing reliable computer systems. The fault-tolerant approach – 1

There are two strategies for increasing the reliability of a computer system. The first, called fault avoidance, is to try and remove the source of every possible fault that could give rise to an error condition. In practice this is not possible and the second strategy, called fault tolerance, is to incorporate various forms of protective redundancy in the form of additional hardware, additional software and time replication. This first part of a two-part tutorial guide to the fault-tolerant approach is a general survey of the many techniques for improving fault tolerance, and comments also on the design of self-checking logic circuits. The second part will look in some detail at one particular implementation (the JPL-Star computer) and concludes with a brief survey of other proposals and implementations