Self-calibration Scheme Research Articles

A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter

The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as Cn=2×Cn−1, the variable capacitor Cn of ADC1 can be updated to be closest to the sum of Cn−1 of ADC1 and Cn−1 of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the Cn of ADC1 can be connected with two of the Cn−1 of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update Cn. This process is iterated, until Cn is in agreement with the sum of two of Cn−1. Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by 21.8 dB and 6.4 dB, respectively.

A self-calibration scheme for two-dimensional free-form probing measurement under the assumption of rigid-body machine kinematic model

A major uncertainty contributor to the on-machine probing is linear axis kinematic errors. This paper proposes a novel self-calibration scheme to separate the workpiece geometry and machine tool kinematic errors from the probed profiles. Many self-calibration schemes have been well developed, but they are limited to either of the straightness, roundness, and two-dimensional (2D) grid point positions, since they require the probed points being in a closed set, as the workpiece is rotated or translated. This paper proposes its extension to a free-form 2D geometry. A key idea is on the assumption that the machine tool’s positioning error is in accordance with the rigid-body kinematic model. It makes linear axis error motions, represented in a look-up table format, be in a closed set. Two experimental case studies are presented. The uncertainty assessment is essential to investigate the effectiveness of the proposed scheme for the given workpiece geometry.

Capacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage Regulation

In this work, a capacitance-to-digital converter (CDC) suitable for direct energy harvesting is introduced. The nW peak power and the ability to operate at any supply voltage in the 0.3-1.8 V range allow complete suppression of any intermediate DC-DC conversion, and hence direct supply provision from the harvester, as demonstrated with a mm-scale solar cell. The proposed CDC architecture eliminates the need for any additional support circuitry, preserving true nW-power operation, and reducing design and integration effort. In detail, the architecture is based on a pair of double-swappable oscillators, and avoids the need for any voltage/current/frequency reference circuit in the oscillator mismatch compensation. The digital and differential nature of the architecture counteracts the effect of process/voltage/temperature variations. A load-agnostic one-time self-calibration scheme compensates mismatch, and can be run from boot to run stage of the chip lifecycle. The proposed self-calibration scheme suppresses any trimming or testing time for low-cost systems, and avoids any input capacitance disconnection requirement. A 180-nm testchip shows 7-bit ENOB down to 0.3 V and 1.37-nW total power, when powered by a 1-mm2 indoor solar cell down to 10 lux (i.e., late twilight).

Constraints on Dark Energy from the CSST Galaxy Clusters

We study the potential of the galaxy cluster sample expected from the Chinese Space Station Telescope (CSST) survey to constrain dark energy properties. By modeling the distribution of observed cluster mass for a given true mass to be log-normal and adopting a selection threshold in the observed mass M 200m ≥ 0.836 × 1014 h −1 M ⊙, we find about 4.1 × 105 clusters in the redshift range 0 ≤ z ≤ 1.5 can be detected by the CSST. We construct the Fisher matrix for the cluster number counts from CSST, and forecast constraints on dark energy parameters for models with constant (w 0CDM) and time dependent (w 0 w a CDM) equation of state. In the self-calibration scheme, the dark energy equation of state parameter w 0 of the w 0CDM model can be constrained to Δw 0 = 0.036. If w a is added as a free parameter, we obtain Δw 0 = 0.077 and Δw a = 0.39 for the w 0 w a CDM model, with a Figure of Merit for (w 0, w a ) of 68.99. Should we have perfect knowledge of the observable-mass scaling relation (“known SR” scheme), we would obtain Δw 0 = 0.012 for the w 0CDM model, and Δw 0 = 0.062 and Δw a = 0.24 for the w 0 w a CDM model. The dark energy Figure of Merit of (w 0, w a ) increases to 343.25. This indicates again the importance of calibrating the observable-mass scaling relation for optically selected galaxy clusters. By extending the maximum redshift of the clusters from to , the dark energy Figure of Merit for (w 0, w a ) increases to 89.72 (self-calibration scheme) and 610.97 (“known SR” scheme), improved by a factor of ∼1.30 and ∼1.78, respectively. We find that the impact of clusters’ redshift uncertainty on the dark energy constraints is negligible as long as the redshift error of clusters is smaller than 0.01, achievable by CSST. We also find that the bias in logarithm mass must be calibrated to be 0.30 or better to avoid significant dark energy parameter bias.

Self-calibrating microring synapse with dual-wavelength synchronization

As a resonator-based optical hardware in analog optical computing, a microring synapse can be straightforwardly configured to simulate the connection weights between neurons, but it faces challenges in precision and stability due to cross talk and environmental perturbations. Here, we propose and demonstrate a self-calibration scheme with dual-wavelength synchronization to monitor and calibrate the synaptic weights without interrupting the computation tasks. We design and fabricate an integrated 4 × 4 microring synapse and deploy our self-calibration scheme to validate its effectiveness. The precision and robustness are evaluated in the experiments with favorable performance, achieving 2-bit precision improvement and excellent robustness to environmental temperature fluctuations (the weights can be corrected within 1 s after temperature changes 0.5°C). Moreover, we demonstrate matrix inversion tasks based on Newton iterations beyond 7-bit precision using this microring synapse. Our scheme provides an accurate and real-time weight calibration independently parallel from computations and opens up new perspectives for precision boost solutions to large-scale analog optical computing.

Self-calibration phase demodulation scheme for stabilization based on an auxiliary reference fiber-optic interferometer and ellipse fitting algorithm.

To solve the problem of light source jitter and asymmetric 3 × 3 coupler, a phase demodulation method with the combination of an auxiliary reference interferometer and elliptic fitting algorithm is proposed, which is verified by simulation and experiment. By introducing additional phase modulation in the auxiliary reference interferometer, the parameters of the sensing arm can be calibrated in real time, which ensures the effective operation of elliptic fitting algorithm in small signal measurement. Consequently, the experiments show that the self-calibration scheme enables a higher signal to noise and distortion ratio with an average increase of 1.65 dB and 10.47 dB compared with the traditional Arctan and cross multiplication differential, respectively. Meanwhile, the self-calibration scheme can also effectively suppress the harmonic distortion, with a total harmonic distortion of -33.64 dB in the case of small signal.

Extrinsic Self-Calibration of the Surround-View System: A Weakly Supervised Approach

An SVS usually consists of four wide-angle fisheye cameras mounted around the vehicle to sense the surrounding environment. From the images synchronously captured by all cameras, a top-down surround-view can be synthesized, on the premise that both intrinsics and extrinsics of the cameras have been calibrated. At present, the intrinsic calibration approach is relatively well-developed and can be pipelined, while the extrinsic calibration is still immature. On one hand, the existing manual calibration schemes are usually reliable, but need to be conducted by professionals in specific sites, which is undoubtedly cumbersome. On the other hand, the majority of the existing self- calibration schemes are based on low-level features and their stability and robustness are usually unsatisfactory. As far as we know, an effective extrinsic self-calibration scheme designed specially for the SVS is still lacking. To fill such a research gap to some extent, we propose a novel self-calibration scheme which follows a weakly supervised framework, namely WESNet (Weakly-supervised Extrinsic Self-calibration Network). The training of WESNet consists of two stages. First, we utilize the corners in a few calibration site images as the weak supervision to roughly optimize the network by minimizing the geometric loss. Then, after the convergency in the first stage, we additionally introduce a self-supervised photometric loss term that can be constructed by the photometric information from natural images for further fine-tuning. Besides, to support training, we totally collected 19,078 groups of synchronously captured fisheye images under various environmental conditions. To our knowledge, thus far this is the largest surround-view dataset containing original fisheye images. By means of learning prior knowledge from the training data, WESNet takes the original fisheye images synchronously collected as the input, and directly yields extrinsics end-to-end with little labor cost. Its efficiency and efficacy have been corroborated by extensive experiments conducted on our collected dataset. To make our results reproducible, source code and the collected dataset have been released at https://cslinzhang.github.io/WESNet/WESNet.html.

Vision-aided self-calibration of a wireless propagation model for crowdsourcing-based indoor localization

Wireless localization method can take advantage of the existing Wi-Fi infrastructures to obtain indoor position information. However, an essential wireless localization bottleneck is the intensive geo-tagging, calibration and updating work of the collected wireless data. In this case, this study develops a vision-aided self-calibration method for wireless localization without manual supervision. This method localizes a pedestrian using a visual coordinate transformation model (V-CTM). The visual location is matched with the simultaneously collected wireless data to automatically generate training data for a wireless propagation model. A wireless self-calibration scheme is proposed to self-train the model using a Bi-LSTM and a principle of separate training. Experiments have demonstrated that the accuracy of the generated training dataset was 0.2 m using the V-CTM. The localization experiment achieved an accuracy of 2 m using the constructed propagation model. Meanwhile, the time and labour consumption for model calibration and updating can be significantly reduced.

A 24 GHz Self-Calibrated All-Digital FMCW Synthesizer With 0.01% RMS Frequency Error Under 3.2 GHz Chirp Bandwidth and 320 MHz/µs Chirp Slope

A 24 GHz self-calibrated all-digital frequency-modulated continuous-wave (FMCW) synthesizer is presented in this article. A multi-bank digitally controlled oscillator (DCO) is employed to provide adequate frequency tuning range and high frequency resolution. A full background self-calibration scheme is proposed to linearize the DCO tuning curve for highly linear and fast chirp generation. An overlap compensator based on an adaptive lookup table (LUT) is utilized to eliminate the frequency overlaps between adjacent DCO tuning bands. The compensation words in the LUT are altered by least-mean-square (LMS) algorithm for robust and precise matching. A ramp tracker, which features real-time ramp tracking with zero steady-state phase error, is employed to estimate and stabilize the frequency ramp. Implemented in 40 nm bulk CMOS, the FMCW synthesizer prototype consumes 28 mW with a 0.26 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area. The maximum chirp bandwidth is 3.2 GHz, corresponding to 13.33% of the center frequency. Measurement results show that the root-mean-square (RMS) frequency error is reduced by 1/10 with self-calibration after 2 ms convergence time. The maximum chirp slope is up to 320 MHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> with 309 kHz RMS frequency error. The minimum RMS frequency error is 7.35 kHz under 5 MHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> chirp slope, corresponding to 0.0002% of the chirp bandwidth.

A self-calibration scheme to monitor long-term changes in linear and rotary axis geometric errors

A calibration scheme of position and orientation errors of rotary axis average lines based on touch-trigger probing is widely available on many commercial five-axis machine tools. Such a measurement is influenced by error motions of both linear and rotary axes. This paper proposes a novel scheme to separately identify linear and rotary axis geometric errors by using a touch-trigger probe and an uncalibrated test piece. Whereas the proposed scheme is based on well-developed self-calibration schemes for the circularity measurement, an original contribution is that it is applied to separate linear and rotary axis geometric errors. Two case studies are presented. First, the proposed tests are performed on the same five-axis machine tool for half a year to observe a long-term change in linear and rotary axis geometric errors. The second case study investigates the influence of room temperature change on linear axis and rotary axis error motions.

A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade

We present the design and test results of a time-to-digital-converter (TDC). The TDC will be a part of the readout Application-Specific Integrated Circuit (ASIC), called endcap timing read-out chip (ETROC), to read out low-gain avalanche detectors (LGADs) for the CMS endcap timing layer (ETL) of high-luminosity large hadron collider (LHC) upgrade. One of the challenges of the ETROC design is that the TDC is required to consume less than 200 μW for each pixel at the nominal hit occupancy of 1%. To meet the low-power requirement, we use a single delay line for both the time of arrival (TOA) and the time over threshold (TOT) measurements without delay control. A double-strobe self-calibration scheme is used to compensate for process variation, temperature, and power supply voltage. The TDC is fabricated in a 65-nm CMOS technology. The overall performances of the TDC have been evaluated. The TOA has a bin size of 17.8 ps within its effective dynamic range of 11.6 ns. The effective measurement precision of the TOA is 5.6 and 9.9 ps with and without nonlinearity correction, respectively. The TDC block consumes 97 μW at the hit occupancy of 1%. Over a temperature range from 23 °C to 78 °C and a power supply voltage range from 1.05 to 1.35 V (the nominal value of 1.20 V), the self-calibrated bin size of the TOA varies within 0.4%. The measured TDC performances meet the requirements except that more tests will be performed in the future to verify that the TDC complies with the radiation tolerance specifications.

A unified scheme for rotation modulation and self-calibration of dual-axis rotating SINS

Rotation modulation and self-calibration are the key techniques for error compensation of the strapdown inertial navigation system, which are generally implemented separately. The 16-sequence scheme is widely used for rotation modulation, while the 18-sequence scheme is used for self-calibration. To reduce the complexity of the practical operations, this paper proposes the combination of the rotation modulation scheme and the calibration path and six corresponding design principles of the scheme with both rotation modulation and self-calibration functions. A 48-sequence rotation scheme is designed, which unifies the scheme for self-calibration and rotation modulation. The simulation and experiment results prove that, compared with the 16-sequence rotation modulation scheme, the proposed 48-sequence scheme can reduce the mathematical platform misalignment angle errors and the sawtooth type velocity errors caused by the misalignments of the inertial measurement unit. Besides, its accuracy of self-calibration is better than that of the 18-sequence self-calibration scheme. The velocity errors and position errors can be reduced by about 0.1 m s−1 and 0.2 nm in 3 d.

Open-Loop Self-Calibration of Position Sensor Offset in SM-PMSM Drive Systems

Field-oriented control (FOC) or vector control is a formidable control strategy for permanent magnet synchronous machines (PMSMs) due to high dynamic torque response. However, FOC requires rotor flux orientation information, typically obtained using a position sensor mounted on the motor. The relative displacement between the position sensor and the rotor zero location is a key calibration required to properly orient the stator field based on the rotor magnetic field. A method is proposed herewith that enables the calibration of this relative offset between the position sensor and the rotor zero that reduces the overall manufacturing floor space and manufacturing time. The proposed scheme exploits hardware and software components that are readily available on the motor-drive system for FOC control. The self-calibration scheme generates a slowly rotating stator flux vector to rotate the motor rotor under the no-load condition to collect information about the position sensor alignment. Lack of a need for specialized measurement in comparison to conventional methods saves and space while reducing the calibration time. The novelty lies in the ability to self-calibrate and, in doing so, reduces resource utilization. Analysis, simulation, and experimental results are provided to validate the proposed methodology.

A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC

This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as foreground operation to achieve low power consumption during operation. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 130nm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s.

A New Variable Forgetting Factor-Based Bias-Compensated RLS Algorithm for Identification of FIR Systems With Input Noise and Its Hardware Implementation

This paper proposes a new variable forgetting factor QRD-based recursive least squares algorithm with bias compensation (VFF-QRRLS-BC) for system identification under input noise. A new variable forgetting factor scheme is proposed to improve its convergence speed and steady-state mean squares error. A new method for recursive estimation of the additive noise variance is also proposed for reliable bias compensation. The mean and mean-square asymptotic behaviors of the algorithm are analyzed and a self-calibration scheme is further proposed to improve the steady-state mean squares error (MSE) due to finite sample effect. Simulations show that the proposed VFF approach offers improved tracking and steady-state MSE performance over the conventional recursive least squares method and its fixed FF counterpart. A linear array architecture is proposed for the realization of this algorithm and several hardware efficient techniques are introduced to avoid the expensive cubic root and division operations required. The proposed algorithm is validated on Xilinx Zynq®-7000 AP SoC ZC702 Field Programmable Gate Array (FPGA). For a 10-tap finite impulse response (FIR) system, the implementation requires only about 11.5k slice look-up table (LUT)s, 4.5k slice registers and 50 DSP48s and it can work up to about 0.58 MHz sample rate with a 200 MHz system clock. The hardware resources are considerably lower than traditional techniques using divider and cubic root realization. The linear array architecture also serves as an attractive alternative to the systolic array in medium to low rate applications due to its reduced hardware usages.

Massive MIMO Self-Calibration: Optimal Interconnection for Full Calibration

In time-division duplexing (TDD) massive multiple-input multiple-output (MIMO) systems, the reciprocity between the downlink (DL) and the uplink (UL) channels can be utilized to infer the DL channel state information (CSI) with the acquired uplink (UL) CSI. However, the end-to-end UL and DL channel reciprocity are broken when there are mismatches in the radio frequency (RF) analog circuits among different antennas at the base station (BS). Without accurate calibration, there will be severe system performance degradation. This paper studies the internal self-calibration scheme to recover all the unknown full calibration coefficients when different BS antennas are interconnected via hardware transmission lines. On the one hand, we derive the calibration performance for an arbitrary interconnection network in closed-form and obtain closed-form Cramer-Rao lower bound (CRLB) expressions when $(M-1)$ transmission lines are consumed and $M$ denotes the total number of BS antennas. On the other hand, we prove that the star interconnection network is optimal for internal full self-calibration due to its lowest CRLB. Numerical simulation are carried out to verify our theoretical analyses and results.

On-Orbit Calibration Approach Based on Partial Calibration-Field Coverage for the GF-1/WFV Camera

The Gaofen-1 (GF1) optical remote sensing satellite is the first in China's series of high-resolution civilian satellites and is equipped with four wide-field-of-view cameras. The cameras work together to obtain an image 800 km wide, with a resolution of 16 m, allowing GF1 to complete a global scan in four days. To achieve high-accuracy calibration of the wide-field-of-view cameras on GF1, the calibration field should have high resolution and broad coverage based on the traditional calibration method. In this study, a GF self-calibration scheme was developed. It uses partial reference calibration data covering the selected primary charge-coupled device to achieve high-accuracy calibration of the whole image. Based on the absolute constraint of the ground control points and the relative constraint of the tie points of stereoscopic images, we present two geometric calibration models based on paired stereoscopic images and three stereoscopic images for wide-field-of-view cameras on GF1, along with corresponding stepwise internal-parameter estimation methods. Our experimental results indicate that the internal relative accuracy can be guaranteed after calibration. This article provides a new approach that enables large-field-of-view optical satellites to achieve high-accuracy calibration based on partial calibration-field coverage.

A New Variable Forgetting Factor-Based Bias-Compensation Algorithm for Recursive Identification of Time-Varying Multi-Input Single-Output Systems With Measurement Noise

This article proposes a new variable forgetting factor (VFF) bias-compensated recursive least-squares (BCRLS) algorithm for the recursive identification of complex time-varying multi-input single-output (MISO) systems with measurement noise. It extends a previously developed real-valued BCRLS algorithm to complex signals and introduces new self-calibrated VFF and noise variance estimation schemes for tracking time-varying systems. The proposed VFF scheme offers faster tracking speed, especially for sudden system changes, while achieving a low steady-state (SS) mean square error (MSE) in a stationary environment. Moreover, the mean and mean square deviation of the complex RLS algorithm under zero-mean white Gaussian output additive noise are performed, from which the variance of the additive noise can be estimated. To mitigate the effect of finite-sample number, a self-calibration scheme is proposed to refine the FF at the SS and hence MSE. Simulations show that the proposed self-calibrated VFF-BCRLS algorithm offers improved tracking speed in sudden system changes and offers smaller MSE over the conventional BCRLS algorithm. Applications to real-world data for pH value prediction of a pH neutralization process and temperature prediction of a glass furnace also demonstrate the effectiveness of the proposed algorithm. The good performance and efficient implementation make it an attractive alternative to other conventional methods for system identification in control and optimization processes and other possible applications.

An Energy-Efficient Multimode Multichannel Gas-Sensor System With Learning-Based Optimization and Self-Calibration Schemes

This paper presents an energy-efficient intelligent multisensor system for hazardous gases, whose performance can be adaptively optimized through a multimode structure and a learning-based pattern recognition algorithm. The multimode operation provides control capability on the tradeoff relationship between accuracy and power consumption. In-house microelectro-mechanical (MEMS) devices, with a suspended nanowire structure, are manufactured to provide desired characteristics of small size, low power, and high sensitivity. Pattern recognition to combine the dimensionality reduction and the neural network is adopted to improve the selectivity of MEMS gas sensors. Moreover, potential deviations in sensing characteristics are calibrated through a proposed self-calibration zooming structure. Reconfigurable circuits for these key features are integrated into an adaptive readout integrated circuit which is fabricated in a 180-nm complementary metal-oxide semiconductor process. For its system-level verification, a wireless multichannel gas-sensor system prototype is implemented and experimentally verified to achieve 2.6 times efficiency improvement.

An Ultra-High Input Impedance Analog Front End Using Self-Calibrated Positive Feedback

This paper presents circuit techniques for ultra-high input impedance analog front end (AFE). In order to boost input impedance, various on- and off-chip parasitic capacitances are cancelled using an active shield and negative capacitance technique. To maximize the cancellation, a self-calibration scheme with active shield replica is proposed for positive feedback-based negative capacitance, which settles at the boundary between stable and unstable states in calibration mode. A prototype IC fabricated in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS achieves an input impedance of 50 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{G}\Omega$ </tex-math></inline-formula> at 50 Hz, equivalent to 60-fF capacitance, while consuming 289 nW from 0.8-V supply. The proposed AFE is applied to heart-rate monitoring using 1-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> dry electrodes over clothes without any straps.