Self-aligned Top-gate Structure Research Articles

Enhanced Stability Under Positive Bias Temperature Stress in Oxide Thin Film Transistors with Double Gate Structure By Improving Bottom Channel Interface

Recently, oxide TFTs have been widely applied not only to TVs and monitors, but also to mobile products such as smartphones and smartwatches. In particular, since oxide TFTs exhibit ultra-low leakage current [1], it became an indispensable technology to reduce power consumption through low-frequency driving. On the other hand, as the resolution of display panels increase and high-speed driving of 120 Hz or more becomes the standard, the scan-on-time gradually shortens. Therefore, it is essential to increase the on-current of the oxide TFT to satisfy high-speed driving requirements in high-resolution displays. As a method of increasing the on-current, a double gate structure using both the top and bottom channels of the oxide semiconductor as shown in Figure 1 has been proposed. Although the on-current is improved, the double gate structure has a problem in that the Positive Bias Temperature Stability (PBTS) is significantly deteriorated compared to the TFT of the top single gate structure. We will discuss the causes of the reliability degradation of the double gate structure and how to improve it.In this paper, self-aligned top gate (SA TG) device structures are considered as shown in Figure 1. After patterning the bottom metal layer (BML) to serve as a bottom gate, a buffer layer is deposited. IGZO film with conventional composition was deposited through sputtering and then gate insulator was deposited via PECVD. A self-aligned top gate structure is formed by patterning the gate electrode and then using the pattern to form an n+IGZO region. After depositing interlayer dielectric (ILD), source/drain electrodes are connected to n+ IGZO through contact holes.Figure 2(a) and 2(b) show the change in transfer characteristics of top single and double gate IGZO TFTs as a function of PBTS duration, respectively. The devices were evaluated in air using a gate bias of Vgs = + 20 V, temperature of 70℃ for a total stress time of 8,000s. As shown in Figure 2, we can see that the Vth shift of the double gate TFT is much larger than that of the top single gate TFT. Since the double gate structure uses both the top and bottom channels of the oxide semiconductor, it is necessary to determine which side of the channel is the main cause of deterioration. Figures 2(c) and 2(d) show PBTS results when bias stress is applied only to the top gate and only to the BML using a 4-terminal TFT. Under the condition of applying a stress voltage to the top gate, excellent reliability characteristics were shown, similar to the results of the top single gate structure. However, under conditions where the stress voltage is applied only to the BML, significant shift of Vth is observed. The difference in deterioration of the top and bottom channels can be interpreted as a difference in the density of excess oxygen defects, which act as electron trap sites [2-3]. During the process of depositing the IGZO film through sputtering, many excess oxygen defects may occur at the bottom interface of the insulating film due to the ion bombardment. As the IGZO film is gradually deposited, the amount of defects accumulated at the bottom interface increases. Meanwhile, the excessive oxygen defect concentration at the top interface can be passivated by hydrogen introduced during gate insulator deposition via PECVD.Figure 3 shows the PBTS results for the top single gate and double gate structures as a function of IGZO deposition power. As the sputtering power decreases, the amount of Vth shift for the top single gate remains nearly constant, while the amount of Vth shift for the double gate structure improves dramatically. It is presumed that the reduction in ion bombardment energy during IGZO deposition leads to decrease in excess oxygen defects accumulated at the interface between IGZO and the bottom insulating film.In summary, reducing IGZO deposition power significantly improves PBTS reliability in double gate structures. This improvement is attributed to reduction of excess oxygen defects accumulated at the bottom channel interface, as inferred from the difference in PBTS results for the top single gate and double gate structures. Reference [1] K.Kato et al. Jpn.J. Appl. Phys. 51(2012) 021201[2] S.Choi et al. IEEE Electron Device Lett., vol. 38, no. 5, pp. 580 (2017)[3] D.H.Kim et al. J.SID, 25/2, p.98 (2017) Figure 1

Self-Aligned Top-Gate Structure in High-Performance 2D p-FETs via van der Waals Integration and Contact Spacer Doping.

The potential of 2D materials in future CMOS technology is hindered by the lack of high-performance p-type field effect transistors (p-FETs). While utilization of the top-gate (TG) structure with a p-doped spacer area offers a solution to this challenge, the design and device processing to form gate stacks pose serious challenges in realization of ideal p-FETs and PMOS inverters. This study presents a novel approach to address these challenges by fabricating lateral p+-p-p+ junction WSe2 FETs with self-aligned TG stacks in which desired junction is formed by van der Waals (vdW) integration and selective oxygen plasma-doping into spacer regions. The exceptional electrostatic controllability with a high on/off current ratio and small subthreshold swing (SS) of plasma doped p-FETs is achieved with the self-aligned metal/hBN gate stacks. To demonstrate the effectiveness of our approach, we construct a PMOS inverter using this device architecture, which exhibits a remarkably low power consumption of approximately 4.5 nW.

Scaling carbon nanotube field effect transistors to 30 nm channel length on pretreated PET

With the extensive application of flexible circuits to artificial intelligence (AI) and the internet of things (IoT), high requirements have been promoted for the integration and miniaturization of flexible circuits. However, the vast majority of transistors on flexible substrates reported so far have micrometer-level channel length (Lch), seriously affecting the integration abilities of flexible circuits. In this work, we explore the scaling behaviors of flexible carbon nanotube field effect transistors (CNT FETs) by fabricating p-type flexible CNT FETs with Lch varying from 2 μm to 70 nm on polyethylene terephthalate (PET) substrates. The improved width-normalized on-state current (Ion/Wch), transconductance (gm) and near-constant gate efficiency indicate that CNTs have great potential in constructing ultra-small flexible FETs. Additionally, we fabricate a CNT FET with a 30-nm channel length on a cleaned PET substrate using a self-aligned top-gate structure; this CNT FET can achieve a high on-state performance of 103 μA/μm when Vds = −0.8 V. The pitch size of the device is 230 nm, which is the smallest size of flexible transistors so far. Even with deep submicron and nanometer channel lengths, the yields of flexible CNT FETs can reach 60% (33/56); which is benefiting from the pretreated substrate, demonstrating the potential for large-scale production.

Electrical Performance Enhancement of Fully Solution-processed Amorphous In-Zn-O Thin-Film Transistor via Argon Plasma Treatment

Amorphous oxide semiconductors are intensively studied nowadays due to its excellent material characteristics, such as high mobility, high optical transparency, large area uniformity, and low processing temperature which enable flexible device application [1]. Solution approach is a promising method over conventional vacuum process, because of its simplicity and versatility with high material utilization which can minimize fabrication cost [2]. To optimize for application in flexible substrates, reduction of process temperatures to <400oC is an important requirement. Plasma treatment can be used to modify thin-film properties and device characteristics by modulating carrier concentration and density of oxygen vacancies [3]. Argon plasma treatment can improve reliability, as carbon concentration on the surface can be reduced, and oxidation enhancement on the surface can be achieved. This research aims to study the effect of plasma treatment on the stability of fully solution processed amorphous Indium Zinc Oxide (a-IZO) thin-film transistor (TFT).Our fully solution processed a-IZO TFTs were fabricated with a self-aligned top gate structure at a maximum fabrication temperature of 300oC. Initially, IZO precursor was spin-coated on Si/SiO2 substrate. Then, fluorinated-polysilsesquioxane (F-PSQ) was deposited with a thickness of ~200 nm which act as a gate-insulator, followed by an IZO layer to be transformed as conducting electrode after treatment. Self-aligned patterning, gate etching, and gate insulator etching were then performed. Lastly, Argon plasma treatment is performed via inductively coupled plasma (ICP), using reactive ion etching SAMCO 10-ip equipment for 5 seconds at room temperature with an ICP power, bias power, and working pressure of 300 W, 100 W, and 5 Pa, respectively. The Argon flow rate was also varied at 100, 75, and 50 sccm. The IZO TFT without plasma treatment was denoted as-fabricated sample. After plasma treatment, exposed IZO layers transform as source/drain and gate. TFT structure before and after plasma treatment can be seen in Fig. 1.Film surface morphology was studied using atomic force microscopy. As Argon concentration increased, the exposed IZO surface became rougher. We also checked the transfer characteristics, performed cyclic measurement, and bias stress tests. Transfer characteristics of TFTs with 90µm width and 10µm length were examined at several drain voltages (Vd = 0.1 V, 5.0 V, and 9.9 V) by a semiconductor parameter analyzer. Transfer curves for as-fabricated and after Ar-75 plasma treatment are shown in Fig 1. As-fabricated sample shows poor switching characteristics because of inactivated source/drain and gate electrodes. After plasma treatment, TFTs show superb characteristics which possibly happened because of changes in the metal-oxide bond formation which increased the conductivity in exposed area. The mobility significantly increased to 31.12 cm2/Vs, with a Vth= -0.3 V and subthreshold swing of 0.28 V/dec for Ar-75 sccm. TFT yield was evaluated by measuring 8 TFTs for each sample. Average mobility for Ar-50, Ar-75, and Ar-100 is 20.30 cm2/Vs, 22.93 cm2/Vs, and 19.88 cm2/Vs, respectively. The mobility increase corresponded to the thin-film quality improvement caused by change in VO and surface roughness [4]. However, excessive Argon gas flow also tend to make samples more conductive.To investigate device stability, positive bias stress (PBS, stress V g= 10 V) and negative bias stress (NBS, stress V g= -10 V) was performed for 2,000s. Lower on-current for all samples were observed as bias stress duration increased. A threshold voltage shift (∆Vth) for Ar-50, Ar-75, and Ar-100 of 0.2 V, -0.3 V, and 0.6 V, respectively after PBS, and 1.4 V, 2.9 V, and 0.7 V, respectively after NBS was observed. We expect that improvement via plasma treatment is due to two main factors. First, ion bombardment caused surface improvement and activated the electrode. Second, the chemical reaction induced by plasma treatment changed the metal-oxide bonds formation [5-6]. Thus, fully solution-processed a-IZO TFT with high mobility up to 31.12 cm2/Vs was achieved by Ar-75 plasma treatment, which also led to better stability under bias stress. These results show that performance enhancement of fully-solution processed a-IZO TFT by plasma treatment has a large potential for future low-temperature flexible device applications.Acknowledgment:This research was supported by JSPS Kakenhi Grant no. 22K14291. The authors thank Nissan Chemical Corporation for providing the IZO precursor solution.

(Invited) High Performance Fully Solution Processed Transistors Towards Flexible Sustainable Electronics

High performance fully solution-processed amorphous InZnO (a-IZO) thin-film transistors (TFT) were fabricated using low temperature processes such as ultraviolet (UV) treatment, excimer laser annealing (ELA), continuous wave (CW) laser irradiation, and Ar plasma treatment. By employing a self-aligned top-gate structure, these processes can selectively functionalize the IZO semiconductor into conductive electrodes. Thus, a single IZO layer can simultaneously act as both the channel and source/drain electrode. Depending on the low temperature process employed, mobilities of up to 40 cm2 V-1 s-1 can be achieved with low turn on-voltage of -0.4 V and subthreshold swing of 0.2 V dec-1 which is comparable to TFTs fabricated by vacuum process. The low temperature approach also enabled the fabrication of fully solution processed a-IZO TFTs on flexible substrates. Comprehensive analysis of several characterization results suggests that both fluorine and oxygen vacancies play a major role in the high performance fully solution processed a-IZO TFTs.

Control of Hydrogen Concentration in Ingazno Thin Film Using Cryopumping System

Recently, amorphous metal-oxide semiconductors (AOSs) such as indium gallium zinc oxide (IGZO) have attracted great attention with their lower power consumption and higher mobility than amorphous silicon in the display field. However, the threshold voltage (Vth) shift of IGZO thin film transistor (TFT) caused by their poor reliability leads to the drop panel luminance. Therefore, improvement of IGZO TFT reliability is necessary, which is largely influenced by oxygen vacancy and hydrogen. In particular, hydrogen has shown different roles inside the IGZO active layer by hydrogen concentration. At lower concentration, the hydrogen passivation of oxygen deficiency region induces the improvement of initial electrical characteristics and reliability [2]. Meanwhile, Vth shift and degradation reliability are generated at higher concentration owing to the hydrogen related defect states [3]. Therefore, controlling excess hydrogen is necessary for reliability enhancement.In this work, IGZO thin film was fabricated by cryopumping system instead of a turbo molecular pump (TMP) for radio frequency sputtering to reduce hydrogen concentration. Cryopump is an adsorption type that enables excellent evacuation ability of hydrogen and moisture taking up most of the partial pressure in high vacuum. As a result, deposition of IGZO thin film with lower hydrogen impurity is available. The hydrogen concentration in the IGZO thin film using both cryopump and TMP was quantitatively analyzed by elastic recoil detection (ERD) analysis. Then, electrical characteristics of the self-aligned top-gate structure TFTs fabricated by both pumps were measured with bias stress conditions.To sum up, we showed the improved reliability of IGZO TFT by controlling excess hydrogen using cryopumping system. Fig.1. (a) Schematic of RF magnetron sputtering process with cryopump. (b) TOF-SIMS depth profiles of hydrogen concentration in IGZO film using TMP and cryopump Acknowledgment This work was supported by the Korea Evaluation Institute of Industrial Technology(KEIT) grant funded by the Korea government (MOTIE) (No. 2021-11-1283) References Chung, Ui-Jin, et al. "15‐1: Invited Paper: Manufacturing Technology of LTPO TFT." SID Symposium Digest of Technical Papers. Vol. 51. No. 1. 2020.Hanyu, Yuichiro, et al. "Hydrogen passivation of electron trap in amorphous In-Ga-Zn-O thin-film transistors." Applied Physics Letters 103.20 (2013): 202114.Mativenga, Mallory, et al. "Origin of light instability in amorphous IGZO thin-film transistors and its suppression." Scientific reports 11.1 (2021): 1-12 Figure 1

Cation Composition-Dependent Device Performance and Positive Bias Instability of Self-Aligned Oxide Semiconductor Thin-Film Transistors: Including Oxygen and Hydrogen Effect.

Amorphous oxide semiconductor transistors control the illuminance of pixels in an ecosystem of displays from large-screen TVs to wearable devices. To satisfy application-specific requirements, oxide semiconductor transistors of various cation compositions have been explored. However, a comprehensive study has not been carried out where the influence of cation composition, oxygen, and hydrogen on device characteristics and stability is systematically quantified, using commercial-grade process technology. In this study, we fabricate self-aligned top-gate structure thin-film transistors with three oxide semiconductor materials, InGaZnO (In/Ga/Zn = 1:1:1), In-rich InGaZnO, and InZnO, having mobility values of 10, 27, and 40 cm2/V·s, respectively. Combinations of varied amounts of oxygen and hydrogen are incorporated into each transistor by controlling the fabrication process to study the effect of these gaseous elements on the physical nature of the channel material. Electrons can be captured by peroxy linkage (O22-) or undercoordinated In (In* to become In+), which are manifested in the extracted subgap density-of-states profile and first-principles calculations. Energy difference between electron-trapped In+ and O22- σ* is the smallest for IGZO, and In+-O22- annihilation occurs by electron excitation from the subgap In+ state to the O22- σ*. Furthermore, characteristic time constants during positive bias stress and recovery reveal the various microscopic physical phenomena within the transistor structure between different cation compositions.

Remarkably stable high mobility self-aligned oxide TFT by investigating the effect of oxygen plasma time during PEALD of SiO2 gate insulator

Oxide thin-film transistors (TFTs) should be manufactured with high mobility and stability based on a self-aligned top-gate structure to drive high-end displays. In this study, the effect of oxygen plasma time over one cycle of plasma-enhanced atomic layer deposition (PEALD) SiO2 on the properties of top-gate oxide TFTs was investigated systemically. The subsurface reaction of oxygen plasma causes a difference in oxygen vacancy (Vo). In addition, hydrogen incorporation also differs according to plasma time. Considering Vo and hydrogen are donors, tendency of electric properties could be explained. These surface reactions and atomic incorporation also induce differences in the positive bias temperature stress (PBTS) stability. Based on oxygen plasma time of 2.0 s, a positive shift in threshold voltage (Vth) due to interfacial degradation was observed when the plasma was longer, while an abnormal negative shift due to H+ drift was observed when it was shorter. When the oxygen plasma time is 2.0 s, the TFT was free from the deterioration of the interface and SiO2. Based on this condition, a self-aligned TFT with superior performance including a high mobility of 31.1 cm2/Vs, positive Vth and high stability of 0.016 V shifting during the PBTS was fabricated successfully.

Positive Bias Stress Instability of InGaZnO TFTs With Self-Aligned Top-Gate Structure in the Threshold-Voltage Compensated Pixel

The instability induced under positive gate-bias stress (PBS) in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with self-aligned top-gate coplanar structure is investigated under the threshold-voltage $({V}_{T})$ compensated pixel scheme in the backplane of organic light-emitting diode displays and compared with that under a constant-PBS scheme . Based on the investigation, which combines the extraction of density of states, the decomposition of ${V}_{T}$ shift ( $\Delta {V}_{T}$ ), and technology computer-aided design, the unreleased electric field across the gate insulator (GI) and the maintained electron concentration are observed under the ${V}_{T}$ -compensated PBS condition. Indeed, the main difference between the two schemes originates from increasingly activated electron trapping within the GI deep-level traps and from the excessive oxygen-related peroxide bond-breaking in the a-IGZO-active film, i.e., O22− + $2 {e}^{-} \to$ O2− + O2−. Although the latter is quantitatively much smaller than the former, the two mechanisms are closely related to each other and should be jointly optimized. This is because a large amount of oxygen interstitials can generate a high density of GI electron traps. Since the GI deep-level trapping results in noticeable $\Delta {V}_{T}$ with an increase in PBS time, our results suggest that the $\Delta {V}_{T}$ should be seriously underestimated with respect to either the estimation of pixel lifetime or the assessment of ${V}_{T}$ -compensated pixel-circuit schemes, if the reliability/acceleration test relies only on the constant-PBS-based single-TFT device test.

Influence of the Gate/Drain Voltage Configuration on the Current Stress Instability in Amorphous Indium-Zinc-Oxide Thin-Film Transistors With Self-Aligned Top-Gate Structure

The influence of ${V}_{\text {GS}}/{V}_{\text {DS}}$ condition on the current stress (CS) instability in amorphous InZnO thin-film transistors (TFTs) with the self-aligned top-gate structure is comprehensively analyzed and quantitatively validated by consolidating: 1) the ${I}$ – ${V}$ and ${C}$ – ${V}$ characteristics; 2) the extraction of density of states; 3) the decomposition of threshold voltage shift ( $\Delta {V} _{T}$ ); and 4) the computer-aided design simulation. It has been found that in a high ${V}_{\text {GS}}$ and low ${V}_{\text {DS}}$ CS condition, electron trapping into the gate insulator globally occurs. However, these effects are combined with a local electron trapping into gate insulator in the source region and the generated peroxide defects in the drain region under a high ${V}_{\text {DS}}$ and low ${V}_{\text {GS}}$ CS condition. The peroxide formation that is followed by the donor generation is clearly distinguished by the activation energy of 0.49 eV from the oxygen vacancies ionization which has been widely modeled for explaining the donor creation in amorphous oxide semiconductor TFTs.

Investigation of Hump Effect of Amorphous In-Ga-Zn-O Thin-Film Transistor Using Scanning Capacitance Microscopy

We investigated the hump effect, which is induced by positive gate-bias stress, of an amorphous In-Ga-Zn-O thin-film transistor with the self-aligned top-gate structure. By applying scanning capacitance microscopy to the transistor with the hump effect, we directly detected a partial increase of carrier density at the channel edges in the channel width direction. The width of the high-carrier-density regions was approximately ${1}\,{\mu \text {m}}$ at each side edge, which is consistent with the estimation by electrical measurements. Such high-carrier regions at the channel edges can act as parasitic transistors with a more negative threshold voltage, generating the hump in the transfer characteristics. Our results support the idea that the hump effect is derived from the parasitic transistors at the channel edges directly and show that the scanning capacitance microscopy provides complementary information to the electrical measurements and is an effective tool to evaluate the hump effect.

Nanometer-Scale Oxide Thin Film Transistor with Potential for High-Density Image Sensor Applications

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

Source/Drain Formation of Self-Aligned Top-Gate Amorphous GaInZnO Thin-Film Transistors by $\hbox{NH}_{3}$ Plasma Treatment

The source/drain region of amorphous GaInZnO thin-film transistor with self-aligned top-gate structure was defined by simple NH3 plasma treatment instead of complicated processes, such as ion implantation and activation. When the source/drain region of active layer was exposed to NH3 gas plasma, the series resistance of the transistor decreased considerably. It exhibited electrical properties, such as a field-effect mobility of 6 cm2/V middots, a threshold voltage of 0.21 V, and a subthreshold swing of 0.23 V/dec.