Self-aligned Technique Research Articles

A simple and practical jump error removal method for fringe projection profilometry based on self-alignment technique.

The code-based method is one of the frequently adopted fringe projection profilometry techniques because of its robustness and high speed. However, the abnormal jump errors caused by the misalignment between the wrapped phase and the fringe order impact the phase unwrapping quality and are more serious in binary defocusing measurement with significant defocusing. This paper proposes a self-alignment technique (SAT) with high speed, no additional patterns, and no accuracy loss to eliminate such jump errors. After analyzing the relation between the grating changes and the misalignment, we designed an assist-code that can perfectly align with the wrapped phase even in significant defocusing. After that, this assist-code is used to adjust the misalignment and eliminate the jump errors. The comparison between the median filter and the proposed SAT method in simulations and experiments demonstrates that the proposed SAT method has the ability to completely remove jump errors for complex textures and step-height objects, even in significant defocusing, indicating its potential to be applied to other phase unwrapping fields, e.g., color-based methods with color coupling problems.

A novel fabrication of TDMOSFETs using two-step trench etching and twice self-alignment technique

ABSTRACTA new fabrication method employing two-step trench etching and twice self-alignment technique was developed to obtain high cell density trench power MOSFETs by using only three mask steps. This method was implemented to increase cell density, to decrease on-resistance and to improve leakage current characteristics. The trench DMOSFETs with 1.6 μm cell pitch and 140 Mcell/in2 cell density were fabricated. The specific on-resistance of the device is about 0.48 mΩ˖cm2 with the breakdown voltage of 43 V.

무인항공기용 관성/위성/레이더 결합 정밀 복합항법장치의 개발 및 성능평가

Development of a high-precision hybrid navigation system for UAVs and its performance evaluation results are described in this paper. The pilot of a UAV cannot determine the state of the aircraft except for the provided sensor measurements. Therefore, the navigation system for the vehicle must provide the position, velocity, and attitude of the system with high accuracy and stability. To achieve these requirements, a navigation-grade inertial navigation system (INS), global navigation satellite system (GNSS), and radar tracking system are integrated to develop a high-precision hybrid navigation system. Moreover, three essential algorithms are applied to the system, including a time-saving self-alignment technique that is based on the virtual initial position, an approach to improve the numerical stability of an indirect Kalman filter with delayed measurements, and a radar-aided navigation algorithm. The performance of the developed system regarding the navigation accuracy and stability is analyzed through ground-vehicle tests and captive-flight tests.

Scalable, Modular Three-Dimensional Silicon Microelectrode Assembly via Electroless Plating.

We devised a scalable, modular strategy for microfabricated 3-D neural probe synthesis. We constructed a 3-D probe out of individual 2-D components (arrays of shanks bearing close-packed electrodes) using mechanical self-locking and self-aligning techniques, followed by electroless nickel plating to establish electrical contact between the individual parts. We detail the fabrication and assembly process and demonstrate different 3-D probe designs bearing thousands of electrode sites. We find typical self-alignment accuracy between shanks of <0.2° and demonstrate orthogonal electrical connections of 40 µm pitch, with thousands of connections formed electrochemically in parallel. The fabrication methods introduced allow the design of scalable, modular electrodes for high-density 3-D neural recording. The combination of scalable 3-D design and close-packed recording sites may support a variety of large-scale neural recording strategies for the mammalian brain.

(Invited) High Write Efficiency in Voltage-Control Spintronics Memory (VoCSM) for Saving Energy Consumption of Nonvolatile Memories

MRAM based on spin-transfer-torque (STT) write operations has been intensively developed as a technology for saving energy. During the development of high-density STT-MRAM, issues have arisen that have placed an intrinsic physical limit on the miniaturization of STT-MRAM. Recently, we proposed and developed a voltage-control spintronics memory (VoCSM) that employs the voltage-controlled-magnetic-anisotropy (VCMA) effect for the selection of MTJs and the spin-Hall effect (SHE) for write operations [1]. We achieved high write efficiency in the VoCSM by taking the following approaches: (1) developing a self-aligned VoCSM structure; (2) improving the spin-Hall electrode to have a large spin-Hall angle; and (3) optimizing the magnetic design of the storage layer. The VoCSM in the present study employs in-plane MTJs. The critical switching current Ic0 in this VoCSM is expressed as follows: Ic0 ~ (2e/ħ)αM S t eff{-(H k_eff-H k_eff(V))/2}(w N t N/θ SH) Here, e is the charge of an electron, α is a damping constant, ħ is Planck’s constant divided by 2π, M S is the saturation magnetization, t eff is the effective thickness of the storage layer, H k_eff is the effective perpendicular magnetic anisotropy field, H k_eff(V) is the variation of H k_eff by the applied voltage (V MTJ), w N and t N are respectively the width and thickness of the spin-Hall electrode, and θ SH is the spin-Hall angle. Approach (1) We fabricated a VoCSM consisting of a string of several MTJs on spin-Hall electrodes as shown in Fig. 1. In the self-aligned VoCSM structure, since the width of the spin-Hall electrode and that of the MTJ are same, almost all of the spin-polarized electrons can exert torque on the storage layer. This enabled a large reduction in the Ic of the self-aligned VoCSM [2]. Furthermore, when the spin-Hall electrode was made thinner by using a highly-selective patterning process, Ic was further reduced [3]. Approach (2) We applied a novel amorphous-TaB/ β-Ta spin-Hall electrode in the VoCSM, as shown in Fig. 1. The amorphous TaB exhibits a large spin-Hall angle (θ SH = -0.18) that is twice that of β-Ta, because extrinsic effects likely have a dominant role in the SHE of TaB [4]. We successfully prepared an extremely small magnetic dead layer (DL) of the storage layer with small interface roughness by using the TaB spin-Hall electrode. The estimated interfacial transparency of CoFeB/TaB had a relatively high value of 0.60 due to the extremely small DL. Approach (3) In the precessional switching mode for in-plane MTJs as represented in Fig. 1, since the spins in the storage layer precess from in-plane to out-of-plane, increasing H k_eff has a big impact on lowering Ic. However, the total magnetization M S t eff and H k_eff are correlated significantly with the magnetic design of the device. In particular, although lowering the total magnetization M S t eff has the advantage of lowering Ic, it may also have the effect of decreasing the retention Δ. In this study, we were able to maintain the retention Δ by increasing t eff (i.e. reducing the size of DL) despite the decreased M S. Consequently, from the perspective of lowering Ic, we successfully achieved factors such as high θ SH, self-aligned device structure related to small w N t N, high H k_eff, low α, and low M S. Device properties of the VoCSM By combining the self-aligned fabrication technique with a novel TaB spin-Hall electrode, a quite small value of critical switching current (Ic ~ 79 μA) was achieved despite a relatively large MTJ size (60 nm × 150 nm). We successfully reduced the write current further to 48 μA by the VCMA effect. The write efficiency of the VoCSM without the VCMA effect is about 4 times higher, and furthermore the write efficiency of the VoCSM by using the VCMA effect can reach 8 times higher compared with STT write operations. The VoCSM device also demonstrates high reliability such as a low write error rate (< 1 × 10-8), high endurance (> 1 × 1012 cycles), and large break-down voltage (> 2.5 V). These results indicate that VoCSM could open a path to realizing high-density nonvolatile memories with low power consumption and high-speed read and write operations. This work was partly supported by the ImPACT Program of the Council for Science, Technology and Innovation (Cabinet Office, Government of Japan).

Enabling Large-Area Selective Deposition on Metal-Dielectric Patterns using Polymer Brush Deactivation

Area-selective deposition could be an important self-aligning material-deposition technique to enable future nanoelectronics by accurately placing active materials at previously defined substrate patterns. We describe a robust self-aligning strategy to pattern uniform gold (Au) thin films on only the dielectric areas of prepatterned copper/silicon dioxide (Cu/SiO2) substrates. The use of an amine-terminated polystyrene polymer brush (i.e., PS-NH2) to selectively block micrometer Cu regions of patterned Cu/SiO2 substrates is demonstrated. Following thermal evaporation of ∼35 nm thick Au films on PS-NH2 modified Cu/SiO2 surfaces and subsequent acetic acid etching, large-area selective patterning of Au films on SiO2 regions was achieved. We evaluated the influence of the initial PS-NH2 polymer brush film concentration and etching conditions to optimize the process window for the demonstration of highly successful area-selective deposition on SiO2 surface regions. X-ray photoelectron spectroscopy and scanning...

Damage to amorphous indium-gallium-zinc-oxide thin film transistors under Cl2 and BCl3 plasma

Plasma damage of indium-gallium-zinc-oxide (IGZO) thin film transistor (TFT) was investigated. The IGZO TFT was fabricated and the performance was measured before and after BCl3 and/or Cl2 plasma treatment to evaluate the IGZO damage. The BCl3 and/or Cl2 plasma deteriorated the IGZO TFT performance significantly even after a short exposure time in the plasma. We propose a new wet etching process to remove a source/drain metal without damaging the underlying IGZO layer. The wet etching process can be utilized for the fabrication of IGZO TFT array using a roll-to-roll process via a self-aligned imprint lithography technique.

A V-Shape Optical Pin Interface for Board Level Optical Interconnect

This paper introduces a new interface of an optical pin for Printed Circuit Boards (PCBs), the V-shape cut type which is an innovation from the 90-degree cut type optical pin. The effectiveness is determined by optical characteristics through OptiCAD and by experiment. The simulation used a model of ray tracing analysis which is a one to two (split) connection function model. For the experiment, a Polymer Optical Fibre (POF) V-shape optical pin has been fabricated. It was found that the V-shaped optical pin has a multi-branched function and is applicable to optical interconnection. Full Text: PDF ReferencesMikami, O., et al. Optical pin interface for 90-deg optical path conversion coupling to Printed Wiring Board. in Region 10 Conference (TENCON), 2016 IEEE. 2016. IEEE. CrossRef DeCusatis, C., Data center architectures, in Optical Interconnects for Data Centers. 2017, Elsevier. p. 3-41. CrossRef Duranton, M., D. Dutoit, and S. Menezo, Key requirements for optical interconnects within data centers, in Optical Interconnects for Data Centers. 2017, Elsevier. p. 75-94. CrossRef ITOH, Y., et al., Optical Coupling Characteristics of Optical Pin with 45° Micro Mirror for Optical Surface Mount Technology. Journal of The Japan Institute of Electronics Packaging, 2001. 4(6): p. 497-503. CrossRef Uchida, T. and O. Mikami, Optical surface mount technology. IEICE Transactions on Electronics, 1997. 80(1): p. 81-87. CrossRef Papakonstantinou, I., et al., Low-cost, precision, self-alignment technique for coupling laser and photodiode arrays to polymer waveguide arrays on multilayer PCBs. IEEE Transactions on Advanced Packaging, 2008. 31(3): p. 502-511. CrossRef Nakama, K., et al., Optical connection device. 2006, Google Patents. DirectLink Ramaswami, R., K. Sivarajan, and G. Sasaki, Optical networks: a practical perspective. 2009: Morgan Kaufmann. DirectLink Tong, X.C., Advanced materials for integrated optical waveguides. 2014: Springer. CrossRef

Self-aligned gate-last process for quantum-well InAs transistor on insulator

This paper presents a promising technology to make quantum-well InAs transistors on SiO2/Si substrate by using a self-aligned gate-last fabrication technique. The full self-aligned fabrication process is demonstrated, and the fabricated device is characterized. A 2-D TCAD simulation is then performed based on the experimental data to understand the operation of the InAs transistors. We explore further optimizations for this technology through TCAD simulations, and it is found that with optimizations in materials, device geometry and fabrication, significant boost in RF performances is possible with these devices.

ROTATIONAL MISMATCH OF SELF-ALIGN TIBIAL COMPONENT IN POSTERIOR-STABILIZED (PS) TOTAL KNEE ARTHROPLASTY

Background: Rotational alignment of femoral and tibial prosthesis is one of the important factors for outcomes of total knee arthroplasty (TKA). Rotational malalignment may lead to patellar maltracking, anterior knee pain, femoro-tibial flexion instability and premature wear of the polyethylene inlay. Several studies have demonstrated higher revision rates and less favorable clinical results among patients with rotational malalignment. The transepicondylar axis is widely accepted as the best representation of the functional flexion-extension axis of the knee. On the other hand, no comparable agreement exists for tibial rotational alignment Objectives: The aim of this study was to determine the accurate rotational alignment of components by posterior cruciate lignment substituting TKA using the center-post self-align technique. Method: From January 2007 to May 2009, 54 patients (60 knees) underwent the cemented, posterior ligament substituting TKA using the center-post self-align technique of the tibial component and performed computer tomography postoperatively. The rotational angle between the femoral and tibial components and the rotational variance from the transepicondylar axis were measured. Results: The rotational alignment of femoral components were 90% in the neutral group: 48.3% external rotate (mean 1.15 , range 0.1 – 4.9), 48.3% internal rotate (mean 1.53 , range 0.2 -3.8) and 3.4% were in neutral alignment. The rotation alignment of tibial components were 71.7% in the neutral group: 41.2% external rotate (mean 2.03 , range 0.2 -6.7), 56.7% internal rotate (mean 2.59 , range 0.3 -6.7) and 1.67% had neutral alignment. We found no rotational mismatch between femoral and tibial components in this study. All 60 knees had good patellar tracking by no thumb test technique without lateral released procedure. Conclusion: Femoral component rotations were mostly in the safe zone. Using the center-post self-align technique in posterior cruciate ligament substiting TKA, tibial component rotation was much more varied than the femur. However, all tibial component rotations were in between medial most and medial 1/3 of the tibial tuberble

Sidewall patterning—a new wafer-scale method for accurate patterning of vertical silicon structures

For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that allows for reproducible sub-micrometer resolution local modification along vertical silicon sidewalls. Instead of optical lithography, this method makes smart use of inclined ion beam etching to selectively etch the top parts of structures, and controlled retraction of a conformal layer to define a hard mask in the vertical direction. The top, bottom or middle part of a structure could be selectively exposed, and it was shown that these exposed regions can, for example, be selectively covered with a catalyst, doped, or structured further.

High-Performance Sub-Micrometer Channel WSe2 Field-Effect Transistors Prepared Using a Flood-Dike Printing Method.

Printing technology has potential to offer a cost-effective and scalable way to fabricate electronic devices based on two-dimensional (2D) transition metal dichalcogenides (TMDCs). However, limited by the registration accuracy and resolution of printing, the previously reported printed TMDC field-effect transistors (FETs) have relatively long channel lengths (13-200 μm), thus suffering low current-driving capabilities (≤0.02 μA/μm). Here, we report a "flood-dike" self-aligned printing technique that allows the formation of source/drain metal contacts on TMDC materials with sub-micrometer channel lengths in a reliable way. This self-aligned printing technique involves three steps: (i) printing of gold ink on a WSe2 flake to form the first gold electrode, (ii) modifying the surface of the first gold electrode with a self-assembled monolayer (SAM) to lower the surface tension and render the surface hydrophobic, and (iii) printing of gold ink close to the SAM-treated first electrode at a certain distance. During the third step, the gold ink would first spread toward the edge of the first electrode and then get stopped by the hydrophobic SAM coating, ending up forming a sub-micrometer channel. With this printing technique, we have successfully downscaled the channel length to ∼750 nm and achieved enhanced on-state current densities of ∼0.64 μA/μm (average) and high on/off current ratios of ∼3 × 105 (average). Furthermore, with our high-performance printed WSe2 FETs, driving capabilities for quantum-dot light-emitting diodes (LEDs), inorganic LEDs, and organic LEDs have been demonstrated, which reveals the potential of using printed TMDC electronics for display backplane applications.

Electrically driven, highly efficient three-dimensional GaN-based light emitting diodes fabricated by self-aligned twofold epitaxial lateral overgrowth

Improvements in the overall efficiency and significant reduction in the efficiency droop are observed in three-dimensional (3D) GaN truncated pyramid structures fabricated with air void and a SiO2 layer. This 3D structure was fabricated using a self-aligned twofold epitaxial lateral overgrowth technique, which improved both the internal quantum efficiency and the light extraction efficiency. In addition, a reduced leakage current was observed due to the effective suppression of threading dislocations. While this study focuses primarily on the blue emission wavelength region, this approach can also be applied to overcome the efficiency degradation problem in the ultraviolet, green, and red emission regions.

Enhanced self-mixing interferometry based on volume Bragg gratings and laser diodes emitting at 405-nm wavelengths.

Self-mixing interferometry (SMI) represents a robust, self-aligned technique for metrology applications. Recently, it has been shown that the detection of the frequency-modulated (FM) signal enhances the conventional SMI signal based on the amplitude modulation. Here, an all-optical, simple and effective alternative approach to detect the FM self-mixing signal is presented. We demonstrate the enhanced self-mixing approach using a laser diode emitting at 405nm and a volume Bragg grating (VBG) to map frequency to intensity modulations for further optical detection. Our approach overcomes the spectral range limitation of the edge filtering approach based on molecular absorption filters, since the VBGs can be fabricated at any spectral range.

Scaling Limits of Graphene Nanoelectrodes.

Graphene nanogap electrodes have been of recent interest in a variety of fields, ranging from molecular electronics to phase change memories. Several recent reports have highlighted that scaling graphene nanogaps to even smaller sizes is a promising route to more efficient and robust molecular and memory devices. Despite the significant interest, the operating and scaling limits of these electrodes are completely unknown. In this paper, we report on our observations of consistent voltage driven resistance switching in sub-5 nm graphene nanogaps. We find that such electrical switching from an insulating state to a conductive state occurs at very low currents and voltages (0.06 μA and 140 mV), independent of the conditions (room ambient, low temperatures, as well as in vacuum), thus portending potential limits to scaling of functional devices with carbon electrodes. We then associate this phenomenon to the formation and rupture of carbon chains. Using a phase change material in the nanogap as a demonstrator device, fabricated using a self-alignment technique, we show that for gap sizes approaching 1 nm the switching is dominated by such carbon chain formation, creating a fundamental scaling limit for potential devices. These findings have important implications, not only for fundamental science, but also in terms of potential applications.

Advances in Two‐Dimensional Layered Materials

Advances in Two‐Dimensional Layered Materials

Fabrication of self-aligned multilevel nanostructures

Multilevel three-dimensional nanostructures are essential in many integrated nanoelectronic and nanophotonic applications. With the continued shrinking of critical device dimensions, extremely precise nanoscale overlay is required between multiple individual levels of these integrated devices. Multilevel nanoimprint lithography has been proposed in the literature as a potential solution to this overlay problem. In this context, self-aligned (perfectly aligned) multilevel templates (SAMT) for multilevel nanoimprint lithography are proposed in this article. By combining nanolithography, atomic layer deposition, and highly selective reactive ion etch, SAMTs can enable the fabrication of sophisticated integrated devices. Four specific self-aligned multilevel fabrication techniques have been demonstrated that result in symmetric multilevel structures, bilaterally symmetric multilevel structures, tubular structures, and asymmetric multilevel structures, all in the sub-100nm scale. When used in conjunction with a nanoimprint lithography process, the SAMTs can enable high-throughput patterning of various nanoelectronic and nanophotonic devices using a single patterning step with perfect alignment and overlay. SAMTs further enable large area patterning, such as wafer-scale patterning and roll-to-roll patterning on flexible substrates, without compromising perfect overlay.

Design and Analysis of CMOS Low-Phase-Noise Low-Jitter Subharmonically Injection-Locked VCO With FLL Self-Alignment Technique

Design and analysis of low-phase-noise low-jitter subharmonically injection-locked voltage-controlled oscillator (VCO) with frequency-locked loop (FLL) self-alignment technique is presented in this paper using 90-nm CMOS process. The issue of the narrow locking range for the subharmonically injection-locked VCO (SILVCO) can be resolved over the variations, especially for high subharmonic number and millimeter-wave band, since the control voltage is adaptively adjusted using the proposed innovative method to refer to the subharmonic input frequency. A theoretical model of the SILVCO with FLL self-alignment technique is addressed for the design consideration and phase noise evaluation. With a subharmonic number of 16, the operation frequency of the proposed $K$ -band circuit is from 24 to 26.1 GHz. The measured minimum phase noise at 1-MHz offset and jitter integrated from 1 kHz to 40 MHz are −114.3 dBc/Hz and 56.6 fs, respectively. As the temperature is from 20 °C to 70 °C, the measured deviations of output power, phase noise, and jitter are within 2 dB, 3 dB, and 67 fs, respectively. This paper demonstrates excellent performance and good robustness, and it can be compared with the previously reported state-of-the-art clock generators in silicon-based technologies.

Fabrication and characterization of microsieve electrode array (µSEA) enabling cell positioning on 3D electrodes

Here the fabrication and characterization of a novel microelectrode array for electrophysiology applications is described, termed a micro sieve electrode array (µSEA). This silicon based µSEA device allows for hydrodynamic parallel positioning of single cells on 3D electrodes realized on the walls of inverted pyramidal shaped pores. To realize the µSEA, a previously realized silicon sieving structure is provided with a patterned boron doped poly-silicon, connecting the contact electrodes with the 3D sensing electrodes in the pores. A LPCVD silicon-rich silicon nitride layer was used as insulation. The selective opening of this insulation layer at the ends of the wiring lines allows to generate well-defined contact and sensing electrodes according to the layout used in commercial microelectrode array readers. The main challenge lays in the simultaneously selective etching of material at both the planar surface (contact electrode) as well as in the sieving structure containing the (3D) pores (sensing electrodes). For the generation of 3D electrodes in the pores a self-aligning technique was developed using the pore geometry to our advantage. This technique, based on sacrificial layer etching, allows for the fine tuning of the sensing electrode surface area and thus supports the positioning and coupling of single cells on the electrode surface in relation to the cell size. Furthermore, a self-aligning silicide is formed on the sensing electrodes to favour the electrical properties.Experiments were performed to demonstrate the working principle of the µSEA using different types of neuronal cells. Capture efficiency in the pores was >70% with a 70% survival rate of the cell maintained for up to 14 DIV.The TiSi2–boron-doped-poly-silicon sensing electrodes of the µSEA were characterized, which indicated noise levels of <15 µV and impedance values of 360 kΩ. These findings potentially allow for future electrophysiological measurements using the µSEA.

Switching from weakly to strongly limited injection in self-aligned, nano-patterned organic transistors.

Organic thin-film transistors for high frequency applications require large transconductances in combination with minimal parasitic capacitances. Techniques aiming at eliminating parasitic capacitances are prone to produce a mismatch between electrodes, in particular gaps between the gate and the interlayer electrodes. While such mismatches are typically undesirable, we demonstrate that, in fact, device structures with a small single-sided interlayer electrode gap directly probe the detrimental contact resistance arising from the presence of an injection barrier. By employing a self-alignment nanoimprint lithography technique, asymmetric coplanar organic transistors with an intentional gap of varying size (< 0.2 μm) between gate and one interlayer electrode are fabricated. An electrode overlap exceeding 1 μm with the other interlayer has been kept. Gaps, be them source or drain-sided, do not preclude transistor operation. The operation of the device with a source-gate gap reveals a current reduction up to two orders of magnitude compared to a source-sided overlap. Drift-diffusion based simulations reveal that this marked reduction is a consequence of a weakened gate-induced field at the contact which strongly inhibits injection.